MPF0900AMMA2ES datasheet(169/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

Because the DMS is intended to detect and protect against random failures in the main control logic, such

failures are considered critical and not fixable at the system level. However random conditions may lead to

temporary failures that may return to normal operation before they can be considered to be critical failures.

Each temporary fault condition will cause the DMS to assert the FS0B pin and set the corresponding interrupt. If

the fault condition was cleared before it was considered a critical fault, and the system MCU is still responsive, it

can go ahead and clear the interrupt and proceed to release the FS0B pin to resume normal operation.

A persistent fault condition will cause the DMS to assert the FS0B and take a strong protective action against a

critical fault condition, as defined in the DMS OTP configuration registers.

The DMS provides secondary control of the system safety output (FS0B) and system reset signal (RSTB), to

ensure the system is placed in a known safe state when a safety-critical fault condition is found in the digital

control unit.

During system operation, the main digital control unit (DCU) has full control of the FS0B and RSTB pins. If the

main DCU becomes unresponsive or there is a failure that may affect the ability of the main DCU to detect a

failure, the DMS will take control of the safety outputs and assert the pins to place the system in a safe state.

The power cutoff signals in the DMS block provide direct control of the power stage of the voltage regulators,

allowing the DMS to disable the output of the power supplies in the event of a critical system failure.

Critical faults leading to a non-functional digital controller will result in the DMS forcing a safe state until the

condition is removed and the digital circuit is able to recover logic control.

Critical faults detected by the DMS but still maintaining the main logic operation will result in the DMS forcing

a safe state and requesting the main digital control unit to move into the Deep Fail-safe state (DFS). The PF09

can then exit the DFS state based on the OTP configuration for this state.

14.12.1 DMS safety coverage

The independent power supply (VDIG_DMS) is provided to eliminate common-cause failures with respect to the

main digital supply, allowing the DMS to detect a fault condition in the main digital controller due to a bad VDIG

supply.

The independent DMS clock is provided to eliminate common-cause faults with respect to the main system

clocks, allowing the DMS to detect fault conditions in the main digital controller due to clock drift or stuck-at

condition.

A bidirectional safety handshake protocol (SHS) is provided to verify that the main digital control unit is

responsive. The safety handshake uses key information to verify the integrity of the DMS configuration registers

and the real-time status of the logic signal controlling the voltage monitoring circuits.

The safety handshake protocol is designed in such way that It behaves as a self-redundant mechanism that

is able to check for single-point or latent failures in the main digital control unit, as well as latent failures in the

DMS block itself.

Dedicated input-monitoring signals are also provided to ensure proper operation of key analog blocks that may

result in a single-point or latent failure in the main logic controller. These blocks include the main VDIG_OV

monitoring and the bandgap comparator, providing a higher level of protection against a random fault that could

cause the main digital control unit to become unresponsive, and therefore unable to react.

14.12.2 DMS safety configuration

The severity of the reaction to the various fault conditions is programmable in the main OTP registers. The DMS

configuration registers, however, are passed to and stored in the dedicated DMS logic control unit, to ensure the

DMS block can perform proper monitoring even if the main logic is lost.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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