MPF0900AMMA2ES datasheet(36/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

OTP_SWx_SEQ[7:0] OTP_

LDOx_SEQ[7:0] OTP_GPOx_

SEQ[7:0] OTP_VMONx_

SEQ[7:0] OTP_RSTB_SEQ[7:0]

SWx_SEQ[7:0] LDOx_

SEQ[7:0] GPOx_

SEQ[7:0] VMONx_

SEQ[7:0] RSTB_SEQ[7:0]

Sequence slot

Startup time [µs]

11111111

254

SEQ_TBASE x SLOT254

Table 30. Channel sequence...continued

If the power good verification mechanism is enabled (OTP_PWRUP_CHK = 1), the device requires all the

monitored supplies enabled in the sequence to be within regulation before the RSTB pin can be released.

If RSTB is not programmed in the OTP sequence and OTP_PWRUP_CHK = 0, the RSTB pin will release by

default after the last regulator/GPO/VMON has been enabled.

If RSTB is not programmed in the OTP sequence and OTP_PWRUP_CHK = 1, the RSTB pin will release after

all regulators in the power up sequence are in regulation.

If the _SEQ[7:0] bits of all channels are set to 0x00 (OFF) and a PWRON event is present, the device will power

up in secondary operation. In such a scenario, the device will enter the RUN state without any regulator or

external VMON enabled or GPO pin releasing high.

The secondary device operation is a special use case of the Power-up sequence to address the scenario

where the PF09 is working as a secondary PMIC, and supplies are meant to be enabled by the MCU during the

system operation. In this scenario the RSTB of primary and secondary PMICs are connected together to create

an OR condition in which the RSTB signal to the MCU is released only after all PMICs are up in the RUN state.

The PWRUP_I interrupt is asserted when the time slot of the last regulator in the sequence has ended, to

indicate the end of the Power-up sequence. By default, the PWRUP_M bit is unmasked at power up to ensure

the INTB pin is always asserted to indicate the end of the Power-up sequence to the system MCU.

Upon a power up, readiness of the minimum voltages rails needed for the system to operate is indicated by

the release of the RSTB pin. At this point the MCU may not yet be ready to listen and react to an Interrupt

event, however, if the sequence extends past the release of the RSTB pin, the MCU can use the INTB as the

notification that all system supplies are up and running.

When returning from the STANDBY into the RUN state, the RSTB pin does not generate a transition, therefore

the MCU does not know for sure when the PMIC has successfully changed to the RUN state and is ready for

full operation. By ensuring the PWRUP_I interrupt is not masked upon entering the STANDBY state, the system

can rely on the INTB pin asserting once the device has successfully entered the RUN state to indicate the

system is ready to perform full operation.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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