MPF0900AMMA2ES datasheet(167/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

14.11 Dynamic CRC (DCRC)

The PF09 features a dynamic cyclic redundancy check (DCRC) routine to check the integrity of the functional

and OTP configuration registers. The dynamic CRC is able to detect bit-flips in the configuration registers that

could lead to a potential single-point or latent failure.

A base CRC code is calculated and stored in memory every time a successful I2C transaction is made on the

functional registers. The base CRC will be used as the reference value to compare with the check CRC code

calculated every 5 ms.

If the check CRC code is different from the base CRC code, the dynamic CRC routine is considered a bad

dynamic CRC and the PF09 will generate a DCRC_I interrupt to report the fault condition. The dynamic CRC

interrupt will assert the INTB pin if the interrupt is not masked.

The dynamic CRC routine is performed within the PF09 logic and does not require any interaction with the

system MCU, however, a fault condition in the dynamic CRC will require the MCU to evaluate and try to correct

the fault condition, to ensure proper operation of the PMIC.

A control flag DCRC_FLG bit is provided to help manage a dynamic CRC failure. The DCRC_FLG will be set

when a bad dynamic CRC condition is present, and the MCU must clear the flag by writing a 1 to it after taking

corrective action. When the DCRC_FLG is cleared, the PF09 will perform a new CRC check to ensure the

registers' configuration has been corrected and is able to return to safe operation.

A dynamic CRC fault condition can have two levels of severity:

1. The first level of severity includes all fault conditions affecting any of the functional registers. This type of

fault can be addressed and fixed by the MCU during the SYSTEM ON states.

The second level of severity includes a fault condition affecting any of the OTP configuration registers. This type

of fault cannot be cleared by the MCU directly, and the MCU must take proper action to request a PMIC restart

to force a clean OTP reload at power up.

A dynamic CRC fault condition should be managed as follows:

1. When a dynamic CRC fault condition is present, the PF09 will notify the MCU and set the system into a safe

state by asserting the FS0B pin.

2. The MCU must verify and/or reload the expected configuration in the functional registers before trying to

clear the DCRC_FLG.

3. The MCU must clear the DCRC_FLG to force a new dynamic CRC calculation and read back the flag again.

4. If the DCRC_FLG was successfully cleared, it means the low-severity fault condition has been cleared, and

the MCU can proceed to release the FS0B again.

5. If the DCRC_FLG flag is still present after clearing the DCRC_FLG, it means the high-severity fault is on the

OTP registers and cannot be fixed. In this scenario, the MCU must place the system into a safe state before

it can request a power-down event via the PWRON pin, or by sending a turnoff event via the SYS_CMD

registers (0xA5).

Fault conditions in the OTP registers will be mostly latent failures, therefore it is acceptable to allow the system

to perform a safe turnoff event to avoid a sudden stop of operation causedby the PMIC.

In devices with lower safety integrity level (ASIL B) where the FS0B pin is used as a programmable fault status

output, the dynamic CRC can also drive the FS0B if FS0B_DCRC = 1. This allows the system to prioritize the

dynamic CRC fault condition over a regular interrupt.

The strategy to service the dynamic CRC fault is the same, regardless the mode of operation of the FS0B.

14.12 Digital machine supervisor

In devices targeting high safety integrity levels (ASIL D / SIL 2) with the FS0B operating in an active safe state,

the PF09 features an NXP proprietary digital machine supervisor (DMS) block to ensure the main digital control

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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