MPF0900AMMA2ES datasheet(84/205 Pages) NXP

84 / 205 page

NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

12.8.14 I2C Interface

Communication with the PF09 is done through a standard I2C protocol supporting various speeds to match

various system requirements.

The SDA and SCL pins must be pulled up externally to VDDIO, and the selection of the external pullup resistors

will depend on the maximum speed used in the system, as shown in the table below.

I2C mode

Speed

Pullup resistor

Access mode

Standard mode (Sm)

100 kbit/s

2.2 kΩ to 4.7 kΩ

Standard

Fast mode (Fm)

400 kbit/s

2.2 kΩ to 4.7 kΩ

Standard

Fast mode plus (Fm+)

1 Mbit/s

2.2 kΩ

Standard

High-speed mode (HS)

3.4 Mbit/s

0.8 kΩ

Single-byte “controller code” required

Table 100. I2C mode of operations

The PF09 High-speed mode (3.4 Mbit/s) is compatible with normal I2C devices on the same bus, but requires

the controller to have an active pullup on the clock line, which is enabled during high-speed transfers. All high-

speed transfers must be preceded by a single-byte "controller code" at fast or standard speed, to request the

high-speed target devices to change to high-speed timing rules. This ensures that fast or normal speed devices

will not try to participate in the transfer. For more details on the I2C protocol refer to the I2C-bus specification

and user manual UM10204 available at https://www.nxp.com/.

The PF09 provides full I2C access during the RUN and the monitored STANDBY states. In the low-power

STANDBY state, the PF09 features I2C communication on demand. This allows the PMIC to turn on the internal

clock when an I2C transaction is started by the controller, perform the I2C command, and disable the internal

clock when the bus goes idle, hence allowing the lowest power consumption during the low-power STANDBY

state.

The default I2C device address is set in OTP during the part definition stage via the OTP_I2C_ADD[2:0] bit field.

OTP_I2C_ADD[2:0]

Device address

000

0x08

001

0x09

010

0x0A

011

0x0B

100

0x0C

101

0x0D

110

0x0E

111

0x0F

Table 101. Setting up the I2C device address

During an I2C transaction, the communication will latch after the eighthth bit of the last byte in the package is

sent. If the data sent is not a multiple of eight bits and/or a bad I2C transaction is detected, the device will ignore

the command and wait for a valid I2C transaction.

The device features a burst modeoperation to read or write multiple contiguous registers without having to start

a new transaction each time.

For more details on the I2C data package structure, please refer to the AN13107, PF series PMIC I2C-bus

communication overview application note found at https://www.nxp.com/.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

Document feedback

84 / 205

MPF0900AMMA2ES датащи(PDF) 84 Page - NXP Semiconductors

MPF0900AMMA2ES датащи(HTML) 84 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL