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MPF0900AMMA2ES датащи(PDF) 51 Page - NXP Semiconductors |
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MPF0900AMMA2ES датащи(HTML) 51 Page - NXP Semiconductors |
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51 / 205 page ![]() NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring Regulator bit to bypass a current limit bit to bypass an undervoltage bit to bypass an overvoltage SW3 SW3_IL_BYP SW3_UV_BYP SW3_OV_BYP SW4 SW4_IL_BYP SW4_UV_BYP SW4_OV_BYP SW5 SW5_IL_BYP SW5_UV_BYP SW5_OV_BYP LDO1 LDO1_IL_BYP LDO1_UV_BYP LDO1_OV_BYP LDO2 LDO2_IL_BYP LDO2_UV_BYP LDO2_OV_BYP LDO3 LDO3_IL_BYP LDO3_UV_BYP LDO3_OV_BYP VAON — VAON_UV_BYP VAON_OV_BYP Table 50. Bits to enable/disable regulators at UV/OV...continued Bypassing the fault detection prevents the specific fault from incrementing the counter, starting the fault timer, or disabling the regulator, if programmed to turn off upon the specific fault. Bypassing the OV/UV fault detection will also prevent the OV/UV condition from asserting the PGOOD pin when the corresponding PG_EN is set to 1. If a specific fault is bypassed, the PF09 will still set the corresponding interrupt bit and the INTB pin will be asserted if the interrupt is not masked. 12.6.2.3 Fault timer To prevent a persistent fault condition, the PF09 provides a programmable fault timer in order to generate a hard fault in the event the soft-fault condition due to an OV,UV or ILIM cannot be cleared. The default value for the duration of the fault timer is set by the OTP_TIMER_FAULT[3:0] bits, however the timer duration can be changed during the system-on states by modifying the TIMER_FAULT[3:0] bits in the I2C registers. TIMER_FAULT [3:0] Fault timer value 0000 Disabled 0001 1 ms 0010 2 ms 0011 4 ms 0100 8 ms 0101 16 ms 0110 32 ms 0111 64 ms 1000 128 ms 1001 256 ms 1010 512 ms 1011 1024 ms 1100 2048 ms 1101 Reserved 1110 Reserved Table 51. Fault timer PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 51 / 205 |
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