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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPF0900AMMA2ES датащи(PDF) 35 Page - NXP Semiconductors |
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MPF0900AMMA2ES датащи(HTML) 35 Page - NXP Semiconductors |
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35 / 205 page  NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring OTP_xxxx_SEQ[7:0] bits. The GPOx_SEQ[7:0] bits for the programmable IOs are valid only if the IO pin is configured as a GPO. (OTP_GPIOx_MODE = 0.) Channel OTP bits Functional bits (power- down sequence) Required condition SW1 OTP_SW1_SEQ[7:0] SW1_SEQ[7:0] – SW2 OTP_SW2_SEQ[7:0] SW2_SEQ[7:0] – SW3 OTP_SW3_SEQ[7:0] SW3_SEQ[7:0] – SW4 OTP_SW4_SEQ[7:0] SW4_SEQ[7:0] – SW5 OTP_SW5_SEQ[7:0] SW5_SEQ[7:0] – LDO1 OTP_LDO1_SEQ[7:0] LDO1_SEQ[7:0] – LDO2 OTP_LDO2_SEQ[7:0] LDO2_SEQ[7:0] – LDO3 OTP_LDO3_SEQ[7:0] LDO3_SEQ[7:0] – VAON OTP_VAON_SEQ[7:0] VAON_SEQ[7:0] – RSTB OTP_RSTB_SEQ[7:0] RSTB_SEQ[7:0] – GPIO1 OTP_GPO1_SEQ[7:0] GPO1_SEQ[7:0] OTP_GPIO1_MODE = 00 or 01 GPIO2 OTP_GPO2_SEQ[7:0] GPO2_SEQ[7:0] OTP_GPIO2_MODE = 00 or 01 GPIO3 OTP_GPO3_SEQ[7:0] GPO3_SEQ[7:0] OTP_GPIO3_MODE = 00 or 01 GPIO4 OTP_GPO4_SEQ[7:0] GPO4_SEQ[7:0] OTP_GPIO4_MODE = 00 or 01 VMON1 OTP_VMON1_SEQ[7:0] VMON1_SEQ[7:0] – VMON2 OTP_VMON2_SEQ[7:0] VMON2_SEQ[7:0] – Table 29. List of channels with selectable power-up sequencing The _SEQ[7:0] bits set the corresponding channel sequence from 0 to 254. A sequence code of 0x00 indicates that the particular channel is not part of the power-up sequence, that is: • Remains OFF in the case of a regulator • Remains low in the case of a GPO • Remains disabled in the case of an external VMON Regulators, GPIOs and voltage monitors that are not enabled during the power-up sequence can be enabled during the SYSTEM ON states via the functional registers. OTP_SWx_SEQ[7:0] OTP_ LDOx_SEQ[7:0] OTP_GPOx_ SEQ[7:0] OTP_VMONx_ SEQ[7:0] OTP_RSTB_SEQ[7:0] SWx_SEQ[7:0] LDOx_ SEQ[7:0] GPOx_ SEQ[7:0] VMONx_ SEQ[7:0] RSTB_SEQ[7:0] Sequence slot Startup time [µs] 00000000 00000000 Off Off 00000001 00000001 0 SLOT0 00000010 00000010 1 SEQ_TBASE x SLOT1 00000011 00000011 2 SEQ_TBASE x SLOT2 … … … … 11111101 11111101 252 SEQ_TBASE x SLOT252 11111110 11111110 253 SEQ_TBASE x SLOT253 Table 30. Channel sequence PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 35 / 205 |
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