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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPF0900AMMA2ES датащи(PDF) 173 Page - NXP Semiconductors |
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MPF0900AMMA2ES датащи(HTML) 173 Page - NXP Semiconductors |
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173 / 205 page  NXP Semiconductors PF09 Nine-channel power management IC with advanced system safety monitoring 15 PF09 register map 15.1 Functional registers The digital control unit resets the I2C bits differently according to their use and reset type. The following reset types are available in the functional registers: Reset type Description VDIG_POR Bits are reset when the VDIG_POR is crossed on the rising edge. • Full power cycle (VIN remove) • Returning from ULPOFF state Fault flags are intended to hold fault data through a power-on cycle (LPOFF) and a DFS cycle. BIST Bits are reset during LBIST, ABIST or self test. Bits are loaded with the result of the test. SC Bits self-clear after a write. PWRUP_SEQ Reset with default value before starting a Power-up sequence (power on and hard reset) OFF_OTP Bits are loaded directly from the OTP mirror registers. Reset occurs at the following times • Upon entering LPOFF • Right before entering the Power-up sequence • During a hard-reset event. SOFT_RST Reset with default value before starting a Power-up sequence (power on and hard reset) and after a soft reset. SOFT_OTP_RST Bits are loaded directly from the OTP mirror registers. Reset occurs at the following times • Upon entering LPOFF • Right before entering the Power-up sequence • During a hard reset event. • During a soft reset (if programmed to do so) Table 227. I2C register reset conditions Bit type Description R Read-only: writing to this bit will have no effect. W Write-only: reading this bit will return a fixed value. RW Read and write: Can read and write data to this bit RW1C Read current value of the bit, write 1 to clear the bit. Writing 0 will have no effect. RWRO Bit is read/write in the test mode (for debug purposes), and read-only in normal operation. Table 228. I2C bit type definitions ADDR REGISTER DEFAULT BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MSB FS_ID[2:0] DEV_ID[4:0] 0x00 DEVICE_ID 0000_0000 R R R R R R R R MSB DEV_FAM[7:0] 0x01 DEVICE_FAM 0000_1001 R R R R R R R R 0x02 REV_ID MSB FULL_LAYER_REV[3:0] METAL_LAYER_REV[3:0] Table 229. Functional register map PF09 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 1.3 — 16 December 2025 Document feedback 173 / 205 |
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