MPF0900AMMA2ES datasheet(38/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

The OTP_SEQ_TSET[1:0] bits are provided to set the settling timer, to allow regulators to reach regulation after

they have been enabled.

OTP_SEQ_TSET[1:0]

Dynamic sequence settling time

500 µs

1000 µs

2000 µs

4000 µs

Table 32. Dynamic sequence settling time

When regulators and GPIO in the same hierarchical level are enabled, the settling timer is started, and the

voltage regulators will be monitored for OV and UV during and after their turn-on ramp.

If any of the regulators in the current hierarchical level is not able to reach regulation before the settling timer

is expired, the device will detect a power-up failure and start a power-down event right away. See section

Section 12.6.5 for more details.

When all regulators in the same or previous hierarchical level are in regulation, the sequencer will proceed to

the next hierarchical level and restart the settling timer for the following hierarchical level.

When a GPIO is configured as general purpose output (GPO) and enabled in the Power-up sequence, the

device will release the pin in the corresponding hierarchical level and it will start sensing the actual state of the

pin to ensure it has been released properly. If the GPIOx pin is not released properly for longer than the settling

time, the device will detect a power-up failure and start a power-down event right away.

When a VMONx is enabled in the Power-up sequence, the monitor is expected to see the external supply

applied to the pin and in regulation within the settling timer. If the external voltage applied to the VMONx is not

able to reach regulation when the settling timer expires, the device will detect a power-up failure and start a

power-down event right away.

When RSTB is not programmed in a slot in the Power-up sequence, the RSTB is released as soon as the last

regulator in the sequence reaches regulation.

When RSTB is programmed in a slot in the Power-up sequence, the device will release the RSTB in the

corresponding hierarchical level, and it will start sensing the state of the pin to ensure it has been released

properly. In such a scenario, even though the RSTB signal has already been released, the PMIC will not enter

the RUN state until the last regulator has reached regulation properly.

When the device enters the RUN state, it will assert the PWRUP_I interrupt and assert the INTB pin to inform

the MCU that it has finished the Power-up sequence properly.

The device will start monitoring system-on fault conditions only after the dynamic Power-up sequence is

finished. At this point PGOOD can be released, if all regulators in the sequence are within regulation.

12.4 Power down

12.4.1 Turn-off events

Turn-off events may be requested by the MCU (non-PMIC fault related) or may be due to a critical failure of the

PMIC (hard fault condition).

12.4.1.1 Non-PMIC failure turn-off events

When OTP_PWRON_MODE = 0, the device will start a power-down event when the PWRON pin is pulled low.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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