MPF0900AMMA2ES datasheet(19/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

11.2 State descriptions

11.2.1 VIN cold boot initialization

When the VIN is applied for the first time (VIN crossing the VIN_POR_RISE threshold), the PF09 will automatically

perform an initialization sequence prior to evaluating a power-up event. If no power-on event is present after

the initialization sequence, the device will move to the corresponding low-power state based on the mode of

operation of the PWRON pin set in the OTP registers.

If the VAON is configured as an always-on supply, the VAON regulator will be enabled as part of the initialization

sequence to ensure the supply is up in regulation by the time the system is ready to request a power-up event.

In devices targeting a high safety integrity level (ASIL/SIL) where the LBIST routine is available, the logic self-

test routine is performed as part of the fuse loading routine to ensure the logic gates controlling the functional

safety mechanism are healthy at power up.

In devices targeting a quality management (QM) safety integrity level or low safety integrity levels where the

LBIST routine is not be available, the logic controller will proceed to the LPOFF state right after the fuse loading

routine is finished.

During the fuse loading, the OTP registers implement a CRC verification to ensure there are no flip bits at

power-up. If an OTP loading error is detected, the corresponding fault flag (_NOK - Register Address Flags:

0x2D) is asserted high and the system will not be allowed to proceed to normal operation to prevent unsafe

operation.

When the state machine enters the LPOFF state, the device will be ready to evaluate the power-on event to

proceed with the power-up sequence.

Symbol

Description

Min

Typ

Max

Unit

VIN_POR_RISE VIN power-on reset threshold (rising)

2.7

2.8

2.9

VIN_POR_FALL VIN power-on reset threshold (falling)

2.5

2.6

2.7

Table 12. VIN_POR thresholds

11.2.2 ULPOFF state

The ULPOFF (Ultra-low power off) state is provided to allow the PMIC to remain in an OFF condition with

minimum functional operation, minimum quiescent current and the ability to wake up if the PWRON pin is

asserted high.

If the VAON is set as an always-on regulator, the configuration of the VAON regulator is maintained during the

ULPOFF state as long as the VIN does not fall below the VIN_POR_FALL threshold.

When the device successfully disables the internal VDIG supply in the ULPOFF state, it is expected that all

notification flags will be lost and reset to the default state once a wake-up event is present.

11.2.3 LPOFF state

During the LPOFF (Low-power off) state, only the VAON regulator can be enabled if it is configured as an

always-on supply via the OTP configuration. All other system regulators will remain disabled until the power-up

sequence is started.

In the LPOFF state, the PF09 is able to evaluate a power-on event on the PWRON pin, based on the

configuration selected by the OTP_PWRON_MODE bit.

In a system using the PWRON pin in level sensitive mode, the LPOFF state becomes a transitory state upon a

wake-up event detected in the ULPOFF state. This allows the system to take advantage of the lowest quiescent

current in the ULPOFF state when the device is intended to remain in the OFF condition.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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