MPF0900AMMA2ES datasheet(94/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

[2]

The slope rate is calculated as (6.25 [mV] * FREQ [MHz]) / (8 * clocking factor)

In applications where the output capacitance is larger than the recommended value, the SW1_SLOWDVS bit

provides the option to force the ramp-down slope to the slowest discharge speed in order to ensure the output is

able to fully discharge before a new turn-on cycle is started.

The SW1_SLOWDVS bit is reset to 1 at power-up, and the MCU can modify it during the SYSTEM ON states if

the system requires a faster discharge on the SW1 regulator.

SW1_SLOWDVS

Ramp-down DVS

Same as ramp up

1.95 mV/µs

Table 112. DVS ramp-down selection bits

The SW1 regulator is only allowed to request a dynamic voltage change when the default OTP value is set to

be within the DVS range. The DVS range is between 0.65 V and 0.9 V, with an OV/UV threshold of 5 % or wider

and a DVS ramp of 3.9 mV/μs or slower. A voltage configuration outside of the DVS range will be fixed to the

default OTP value, and any voltage change requested via the I2C communication will be ignored to avoid an

invalid configuration.

The OTP_SW1_DVSMAX[3:0] bits are provided to define the maximum high-voltage delta allowed during a

DVS transition. Maximum high-voltage delta is calculated with respect to the default voltage setting selected

by the OTP_VSW1_RUN[7:0] bits to ensure the system is not able to request a voltage change outside of the

selected limits defined for a specific application.

OTP_SW1_DVSMAX[3:0]

SW1 high-voltage delta

0000

0.025 V

0001

0.050 V

0010

0.075 V

0011

0.100 V

0100

0.125 V

0101

0.150 V

0110

0.175 V

0111

0.200 V

1000

0.225 V

1001

0.250 V

1010

0.275 V

1011

0.300 V

1100

0.325 V

1101

0.350 V

1110

0.375 V

1111

0.400 V

Table 113. Maximum DVS selection bits

If the MCU tries to write a voltage value in SW1 higher than the OTP_SW1_DVSMAX[3:0] selection, the

controller will ignore the command and send a DVSMAX_I interrupt. The DVSMAX_I interrupt will assert the

INTB pin if the interrupt is not masked.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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