MPF0900AMMA2ES datasheet(34/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

12.3.2 Power-up events

Upon loading the OTP fuses, the device will evaluate a PWRON event in the LPOFF State based on the

OTP_PWRON_MODE bit.

When OTP_PWRON_MODE = 0, the PWRON pin must be pulled high to generate a power-on event. If the

PWRON pin is low during the LPOFF, the device will return to the ULPOFF until a new wake-up condition is

present.

When OTP_PWRON_MODE = 1, the PWRON pin must see a high to low transition and remain low for as long

as the PWRON_DBNC timer, to generate a power-on event. If the PWRON pin has not experienced a high to

low transition, the device will remain in the LPOFF until a valid PWRON event is present.

Upon a power up event reaching the DBGOFF state, the device will proceed to the power-up sequence only if:

VIN > UVDET

&& TJ is at least 10 °C below the TSD threshold

&& VIN < VIN_OV (unless the OV is disabled or OTP_VIN_OV_SDWN = 0)

&& TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

&& LBIST_STATUS[1:0] is different from “10” (If LBIST enabled)

&& XFAILB pin is released high. (If XFAILB enabled)

12.3.3 Regulator Power-up sequence

The PF09 provides two different ways to power up.

Time-based power up: the system regulators are sequenced up in up to 254 slots, with a constant time

separation between each slot.

Dynamic power up: the system regulators are turned on sequentially only after regulators in the previous

hierarchical level have reached the point of regulation.

The selection of the default Power-up sequence behaviors is done in OTP during the device OTP customization

stage.

12.3.3.1 Time-based power-up

When the OTP_SEQ_MODE = 0, the device will power up in time-based mode.

In the time-based mode, the OTP_SEQ_TBASE[1:0] bits set the default time base for the power-up and power-

down sequencer.

OTP_SEQ_TBASE[1:0]

SEQ_TBASE[1:0]

Sequencer time base [µs]

120

250

500

Table 28. Default sequencer time base

After power-up, the SEQ_TBASE[1:0] bits can be modified during the system-on states in order to change the

sequencer timing during RUN-to-STANDBY transitions as well as during the power-down sequence.

The PF09 controls the power-up sequencing for the switching regulator, LDO regulators, external VMON

inputs, and GPIO pins, as well as controlling the release of the RSTB signal as programmed in the respective

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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