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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 220 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 220 Page - Toshiba Semiconductor |
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220 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-218 4.9 Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK ) Variable 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Unit BUSRQ setup time to CLK tBRC 120 120 120 ns CLK → BUSAK falling edge tCBAL 1.5X + 120 240 195 ns CLK → BUSAK rising edge tCBAH 0.5x + 40 80 65 ns Output buffer off to BUSAK tABA 0 80 0 80 0 80 ns BUSAK to output buffer on tBAA 0 80 0 80 0 80 ns Note 1: Even if the BUSRQ signal goes low, the bus will not be released while the WAIT signal is low. The bus will only be released when BUSRQ goes low while WAIT is high. Note 2: This line shows only that the output buffer is in the off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resistor during bus release, careful design is necessary, as fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal. CLK ALE (Note 1) tBRC tBRC tCBAL tCBAH (Note 2) (Note 2) tBAA tABA AD0 to AD15, A0 to A23, CS0 to CS2 , W R/ , RAS , 0 CAS to 2 CAS BUSRQ BUSAK RD , WR , HWR |
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