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TMP93CS41 датащи(PDF) 216 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 216 Page - Toshiba Semiconductor |
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216 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-214 (2) Write cycle Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. A0 to A15 D0 to D15 CLK X1 A0 to A23 Port output (Note) tCP tWW tDW tWD AD0 to AD15 ALE 0 CAS to 2 CAS WR , HWR RAS WAIT W R/ CS0 to CS2 |
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