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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 218 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 218 Page - Toshiba Semiconductor |
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218 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-216 4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6 and TI7) Variable 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Unit Clock cycle tVCK 8X + 100 740 500 ns Low level clock pulse width tVCKL 4X + 40 360 240 ns High level clock pulse width tVCKH 4X + 40 360 240 ns 4.7 Interrupt and Capture (1) NMI and INT0 interrupts Variable 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Unit NMI , INT0 low level pulse width tINTAL 4X 320 200 ns NMI , INT0 high level pulse width tINTAH 4X 320 200 ns (2) INT4 to INT7 interrupts, capture The INT4 to INT7 input pulse width depends on the CPU operation clock and timer (9-bit prescaler). The following shows the pulse width for each clock. tINTBL (INT4 to INT7 low level pulse width) tINTBH (INT4 to INT7 high level pulse width) Variable 20 MHz Variable 20 MHz System Clock Selected <SYSCK> Prescaler Clock Selected <PRCK1:0> Min Min Min Min Unit 00 (fFPH) 8X + 100 500 8X + 100 500 ns 01 (fs) 8XT + 0.1 244.3 8XT + 0.1 244.3 0 (fc) 10 (fc/16) 128x + 0.1 6.5 128X + 0.1 6.5 00 (fFPH) 1 (fs) (Note 2) 01 (fs) 8XT + 0.1 244.3 8XT + 0.1 244.3 µs Note 1: XT represents the frequency of the low-frequency clock fs. Calculated at fs = 32.768 kHz. Note 2: When using fs as the system clock, fc/16 cannot be selected as the prescaler clock. Output mode/ input rising mode (Input falling mode) tSCY 3 2 1 0 tOHS tOSS Output data TXD Input data RXD Valid Valid Valid Valid 0 1 2 3 tHSR tSRD SCLK SCLK |
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