MNSC140CORE datasheet(20/88 Pages) FREESCALE

20 / 88 page

MSC8122 Technical Data, Rev. 13

1-10

Freescale Semiconductor

Signals/Connections

TT1

Input/ Output Bus Transfer Type 1

The bus master drives this pins during the address tenure to specify the type of the transaction. Some

applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101

and vice versa. In these applications, TT1 functions as read/write signal.

TT[2–4]

CS[5–7]

Input/ Output

Output

Bus Transfer Type 2–4

The bus master drives these pins during the address tenure to specify the type of the transaction.

Chip Select 5–7

Enables specific memory devices or peripherals connected to the system bus.

CS[0–4]

Output

Chip Select 0–4

Enables specific memory devices or peripherals connected to the system bus.

TSZ[0–3]

Input/ Output

Transfer Size 0–3

The bus master drives these pins with a value indicating the number of bytes transferred in the current

transaction.

TBST

Input/ Output Bus Transfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers

eight words).

IRQ1

GBL

Input

Output

Interrupt Request 11

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Global1

When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin

indicates that the transfer is global and should be snooped by caches in the system.

IRQ3

BADDR31

Input

Output

Interrupt Request 31

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Burst Address 311

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

IRQ2

BADDR30

Input

Output

Interrupt Request 21

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Burst Address 301

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

IRQ5

BADDR29

Input

Output

Interrupt Request 51

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Bus Burst Address 291

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR28

Output

Burst Address 28

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR27

Output

Burst Address 27

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

Table 1-5.

DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

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