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MNSC140CORE датащи(PDF) 12 Page - Freescale Semiconductor, Inc

номер детали MNSC140CORE
подробное описание детали  Quad Core 16-Bit Digital Signal Processor
PDF  88 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MNSC140CORE датащи(HTML) 12 Page - Freescale Semiconductor, Inc

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MSC8122 Technical Data, Rev. 13
1-2
Freescale Semiconductor
Signals/Connections
HD0/SWTE
↔
1
D
S
I
/
S
Y
S.
B
U
S
/
E
T
H
E
R
N
E
T
S
Y
S
T
E
M
B
U
S
32
↔ A[0–31]
HD1/DSISYNC
↔
1
1
↔ TT0/HA7
HD2/DSI64
↔
1
1
↔ TT1
HD3/MODCK1
↔
1
3
↔ TT[2–4]/CS[5–7]
HD4/MODCK2
↔
1
5
→ CS[0–4]
HD5/CNFGS
↔
1
4
↔ TSZ[0–3]
HD[6–31]
↔ 26
1
↔ TBST
HD[32-39]/D[32-39]/reserved
↔
8
1
↔ IRQ1/GBL
HD40/D40/ETHRXD0
↔
1
1
↔ IRQ3/BADDR31
HD41/D41/ETHRXD1
↔
1
1
↔ IRQ2/BADDR30
HD42/D42/ETHRXD2/reserved
↔
1
1
↔ IRQ5/BADDR29
HD43/D43/ETHRXD3/reserved
↔
1
1
→ BADDR28
HD[44-45]/D[44-45]/reserved
↔
2
1
→ BADDR27
HD46/D46/ETHTXD0
↔
1
1
↔ BR
HD47/D47/ETHTXD1
↔
1
1
↔ BG
HD48/D48/ETHTXD2/reserved
↔
1
1
↔ DBG
HD49/D49/ETHTXD3/reserved
↔
1
1
↔ ABB/IRQ4
HD[50-53]/D[50-53]/reserved
↔
4
1
↔ DBB/IRQ5
HD54/D54/ETHTX_EN
↔
1
1
↔ TS
HD55/D55/ETHTX_ER/reserved
↔
1
1
↔ AACK
HD56/D56/ETHRX_DV/ETHCRS_DV
↔
1
1
↔ ARTRY
HD57/D57/ETHRX_ER
↔
1
32
↔ D[0–31]
HD58/D58/ETHMDC
↔
1
1
↔ reserved/DP0/DREQ1/EXT_BR2
HD59/D59/ETHMDIO
↔
1
1
↔ IRQ1/DP1/DACK1/EXT_BG2
HD60/D60/ETHCOL/reserved
↔
1
1
↔ IRQ2/DP2/DACK2/EXT_DBG2
HD[61–63]/D[61-63]/reserved
↔
3
1
↔ IRQ3/DP3/DREQ2/EXT_BR3
HCID[0–2]
→
3
M
E
M
C
D
S
I
1
↔ IRQ4/DP4/DACK3/EXT_DBG3
HCID3/HA8
→
1
1
↔ IRQ5/DP5/DACK4/EXT_BG3
HA[11–29]
→ 19
1
↔ IRQ6/DP6/DREQ3
HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3]
→
4
1
↔ IRQ7/DP7/DREQ4
HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/
PWE[4–7]/PSDDQM[4–7]/PBS[4–7]
↔
4
1
↔ TA
HRDS/HRW/HRDE
→
1
1
↔ TEA
HBRST
→
1
1
← NMI
HDST[0–1]/HA[9–10]
→
2
1
→ NMI_OUT
HCS
→
1
1
↔ PSDVAL
HBCS
→
1
1
↔ IRQ7/INT_OUT
HTA
←
1
M
E
M
C
S
Y
S
1
→ BCTL0
HCLKIN
→
1
1
→ BCTL1/CS5
GPIO0/CHIP_ID0/IRQ4/ETHTXD0
↔
1
G
P
I
O
/
T
D
M
/
E
T
H
E
R
N
E
T
/
T
I
M
E
R
S
/
I
2
C
3
↔ BM[0–2]/TC[0–2]/BNKSEL[0–2]
GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
↔
1
1
→ ALE
GPIO2/TIMER1/CHIP_ID2/IRQ6
↔
1
4
→ PWE[0–3]/PSDDQM[0–3]/PBS[0–3]
GPIO3/TDM3TSYN/IRQ1/ETHTXD2
↔
1
1
→ PSDA10/PGPL0
GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
↔
1
1
→ PSDWE/PGPL1
GPIO5/TDM3TDAT/IRQ3/ETHRXD3
↔
1
1
→ POE/PSDRAS/PGPL2
GPIO6/TDM3RSYN/IRQ4/ETHRXD2
↔
1
1
→ PSDCAS/PGPL3
GPIO7/TDM3RCLK/IRQ5/ETHTXD3
↔
1
1
↔ PGTA/PUPMWAIT/PGPL4/PPBS
GPIO8/TDM3RDAT/IRQ6/ETHCOL
↔
1
1
→ PSDAMUX/PGPL5
GPIO9/TDM2TSYN/IRQ7/ETHMDIO
↔
1
GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC
↔
1
De
bug
1
← EE0
GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD
↔
1
1
→ EE1
GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC
↔
1
C
L
K
1
→ CLKOUT
GPIO13/TDM2RCLK/IRQ11/ETHMDC
↔
1
1
← Reserved
GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC
↔
1
1
← CLKIN
GPIO15/TDM1TSYN/DREQ1
↔
1
R
E
S
E
T
1
← PORESET
GPIO16/TDM1TCLK/DONE1/DRACK1
↔
1
1
↔ HRESET
GPIO17/TDM1TDAT/DACK1
↔
1
1
↔ SRESET
GPIO18/TDM1RSYN/DREQ2
↔
1
1
← RSTCONF
GPIO19/TDM1RCLK/DACK2
↔
1
J
T
A
G
1
← TMS
GPIO20/TDM1RDAT
↔
1
1
← TDI
GPIO21/TDM0TSYN
↔
1
1
← TCK
GPIO22/TDM0TCLK/DONE2/DRACK2
↔
1
1
← TRST
GPIO23/TDM0TDAT/IRQ13
↔
1
1
→ TDO
GPIO24/TDM0RSYN/IRQ14
↔
1
GPIO25/TDM0RCLK/IRQ15
↔
1
GPIO26/TDM0RDAT
↔
1
GPIO27/URXD/DREQ1
↔
1
GPIO28/UTXD/DREQ2
↔
1
GPIO29/CHIP_ID3/ETHTX_EN
↔
1
Ded.
Eth.
Net
1
← ETHRX_CLK/ETHSYNC_IN
GPIO30/TIMER2/TMCLK/SDA
↔
1
1
← ETHTX_CLK/ETHREF_CLK/ETHCLOCK
GPIO31/TIMER3/SCL
↔
1
1
← ETHCRS/ETHRXD
Power signals are: VDD, VDDH, VCCSYN, GND, GNDH, and GNDSYN. Reserved signals can be left unconnected. NC signals must not be connected.
Figure 1-1.
MSC8122 External Signals



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