MNSC140CORE datasheet(38/88 Pages) FREESCALE

38 / 88 page

MSC8122 Technical Data, Rev. 13

2-4

Freescale Semiconductor

Specifications

2.5 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and

inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC

timings are based on a 20 pF load, except where noted otherwise, and a 50

Ω transmission line. For loads smaller

than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for

SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider

additional RC delay.

Table 2-4.

DC Electrical Characteristics

Characteristic

Symbol

Min

Typical

Max

Unit

Input high voltage1, all inputs except CLKIN

VIH

2.0

—

3.465

Input low voltage1

VIL

GND

0.4

CLKIN input high voltage

VIHC

2.4

3.0

3.465

CLKIN input low voltage

VILC

GND

0.4

Input leakage current, VIN = VDDH

IIN

–1.0

0.09

µA

Tri-state (high impedance off state) leakage current, VIN = VDDH

IOZ

–1.0

0.09

µA

Signal low input current, VIL = 0.4 V

–1.0

0.09

µA

Signal high input current, VIH = 2.0 V

–1.0

0.09

µA

Output high voltage, IOH = –2 mA,

except open drain pins

VOH

2.0

3.0

—

Output low voltage, IOL= 3.2 mA

VOL

—

0.4

Internal supply current:

•

Wait mode

•

Stop mode

IDDW

IDDS

—

3753

2903

—

Typical power 400 MHz at 1.2 V4

—

1.15

—

Notes:

See Figure 2-1 for undershoot and overshoot voltages.

Not tested. Guaranteed by design.

Measured for 1.2 V core at 25°C junction temperature.

The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No

peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and

all four cores. It was created using CodeWarrior® 2.5. These values are provided as examples only. Power consumption is

application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining

proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of

this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).

Figure 2-1.

Overshoot/Undershoot Voltage for VIH and VIL

GND

GND – 0.3 V

GND – 0.7 V

VIL

VIH

Must not exceed 10% of clock period

VDDH + 17%

VDDH + 8%

VDDH

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