MNSC140CORE datasheet(24/88 Pages) FREESCALE

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MSC8122 Technical Data, Rev. 13

1-14

Freescale Semiconductor

Signals/Connections

1.5 Memory Controller Signals

Refer to the Memory Controller chapter in the MSC8122 Reference Manual for details on configuring these

signals.

IRQ7

INT_OUT

Input

Output

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Interrupt Output

Assertion of this output indicates that an unmasked interrupt is pending in the MSC8122 internal interrupt

controller.

Notes:

See the System Interface Unit (SIU) chapter in the MSC8122 Reference Manual for details on how to configure these pins.

When used as the bus control arbiter, the MSC8122 can support up to three external bus masters. Each master uses its own

set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and

EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or

is not a MSC8122 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU)

chapter in the MSC8122 Reference Manual for details on how to configure these pins. The second and third set of pins is

defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG)

have a dual function. When the MSC8122 is not the bus arbiter, it uses these signals (BR/BG/DBG) to obtain master control of

the bus.

Table 1-6.

Memory Controller Signals

Signal Name

Type

Description

BCTL0

Output

System Bus Buffer Control 0

Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the

value of SIUMCR[BCTLC].

BCTL1

CS5

Output

System Bus Buffer Control 1

Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the

value of SIUMCR[BCTLC].

System and Local Bus Chip Select 5

Enables specific memory devices or peripherals connected to MSC8122 buses.

BM[0–2]

TC[0–2]

BNKSEL[0–2]

Input

Input/ Output

Output

Boot Mode 0–2

Defines the boot mode of the MSC8122. This signal is sampled on PORESET deassertion.

Transfer Code 0–2

The bus master drives these pins during the address tenure to specify the type of the code.

Bank Select 0–2

Selects the SDRAM bank when the MSC8122 is in 60x-compatible bus mode.

ALE

Output

Address Latch Enable

Controls the external address latch used in an external master bus.

PWE[0–3]

PSDDQM[0–3]

PBS[0–3]

Output

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the

address and size of the transaction and the port size of the accessed device.

Table 1-5.

DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

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