MNSC140CORE datasheet(63/88 Pages) FREESCALE

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MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

3-1

Packaging

This section provides information on the MSC8122 package, including diagrams of the package pinouts and tables

showing how the signals discussed in Chapter 1 are allocated. The MSC8122 is available in a 431-pin flip chip-

plastic ball grid array (FC-PBGA).

3.1 Package Description

Figure 3-1 and Figure 3-2 show top and bottom views of the package, including pinouts. To conform to JEDEC

requirements, the package is based on a 23

× 23 position (20 × 20 mm) layout with the outside perimeter

depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the

signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1–2],

CNFGS

, and CHIP_ID[0–3]) are not shown in these figures if there is another signal assigned to the pin after reset.

Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ

lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second

functions (BADDR[29–31], DP[1–7], and INT_OUT) are used.

Table 3-1 lists the MSC8122 signals alphabetically by signal name. Connections with multiple names are listed

individually by each name. Signals with programmable polarity are shown both as signals which are asserted low

(default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is

listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity

are shown in this table only with their default name (asserted low).

Note:

For Ethernet signals multiplexed with the DSI/system Bus (MII and RMII modes only), signals not used by

the RMII mode are reserved when the Ethernet controller is multiplexed with the DSI/system bus and

RMII mode is selected. These reserved signals can be left unconnected. These RMII reserved signals are

not included in Table 3-1, but are indicated in Table 3-2.

Note:

For Ethernet signals multiplexed with the GPIO/TDM signals, signals not used by the RMII or SMII mode

can be assigned to their alternate GPIO or dedicated function, except for GPIO10 and GPIO14. If the

Ethernet controller is enabled and multiplexed with the GPIO signals and SMII mode is selected, GPIO10

and GPIO14 (E21 and F21, respectively) must be left unconnected. These signals are designated as NC (no

connect) in Table 3-1 and Table 3-2.

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