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MNSC140CORE датащи(PDF) 48 Page - Freescale Semiconductor, Inc

номер детали MNSC140CORE
подробное описание детали  Quad Core 16-Bit Digital Signal Processor
PDF  88 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
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MNSC140CORE датащи(HTML) 48 Page - Freescale Semiconductor, Inc

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MSC8122 Technical Data, Rev. 13
2-14
Freescale Semiconductor
Specifications
2.5.5.2 CLKIN to CLKOUT Skew
Table 2-16 describes the CLKOUT-to-CLKIN skew timing.
For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 2-15 to adjust the rise-
to-fall timing values specified for CLKIN synchronization. Figure 2-6 shows the relationship between the CLKOUT
and CLKIN timings.
Table 2-15.
CLKOUT Skew
No.
Characteristic
Min1
Max1
Units
20
Rise-to-rise skew
•VDD = 1.1 V
•VDD = 1.2 V
0.0
0.0
0.95
0.85
ns
ns
21
Fall-to-fall skew
•VDD = 1.1 V
•VDD = 1.2 V
–1.5
–0.8
1.0
1.0
ns
ns
22
CLKOUT phase (1.2 V, 133 MHz)
•
Phase high
•
Phase low
2.8
2.8
—
—
ns
ns
23
CLKOUT phase (1.1 V, 133 MHz)
•
Phase high
•
Phase low
2.2
2.2
—
—
ns
ns
24
CLKOUT phase (1.1 V, 100 MHz)
•
Phase high
•
Phase low
3.3
3.3
—
—
ns
ns
Notes:
1.
A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.
2.
Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
3.
CLKOUT skews are measured using a load of 10 pF.
4.
CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
Figure 2-6.
CLKOUT and CLKIN Signals.
CLKIN
CLKOUT
20
21



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