MNSC140CORE datasheet(25/88 Pages) FREESCALE

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Memory Controller Signals

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

1-15

PSDA10

PGPL0

Output

System Bus SDRAM A10

From the bus SDRAM controller. The precharge command defines which bank is precharged. When the

row address is driven, it is a part of the row address. When column address is driven, it is a part of column

address.

System Bus UPM General-Purpose Line 0

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PSDWE

PGPL1

Output

System Bus SDRAM Write Enable

From the bus SDRAM controller. Should connect to SDRAM WE input.

System Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

POE

PSDRAS

PGPL2

Output

System Bus Output Enable

From the bus GPCM. Controls the output buffer of memory devices during read operations.

System Bus SDRAM RAS

From the bus SDRAM controller. Should connect to SDRAM RAS input.

System Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PSDCAS

PGPL3

Output

System Bus SDRAM CAS

From the bus SDRAM controller. Should connect to SDRAM CAS input.

System Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PGTA

PUPMWAIT

PGPL4

PPBS

Input

Output

System GPCM TA

Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper

operation.

System Bus UPM Wait

An external device holds this pin low to force the UPM to wait until the device is ready to continue the

operation.

System Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

System Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is used as the byte-select for that chip.

PSDAMUX

PGPL5

Output

System Bus SDRAM Address Multiplexer

Controls the system bus SDRAM address multiplexer when the MSC8122 is in external master mode.

System Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

Table 1-6.

Memory Controller Signals (Continued)

Signal Name

Type

Description

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