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8.2 Processor Subsystems

8.2.1 Arm Cortex-A53 Subsystem

The SoC implements one cluster of quad-core Arm® Cortex®-A53 MPCore™, with 32KB L1 instruction, 32KB L1

data, per core and 512KB L2 shared cache.

The Cortex®-A53 cores are general-purpose processors that can be used for running customer applications.

The A53SS is built around the Cortex®-A53 MPCore™ (Arm®-A53 Cluster), which is provided by Arm and

configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus, it delivers high

performance and optimal power management, debug and emulation capabilities.

The A53 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 Instruction

and Data Caches, compatible with Arm®v8-A architecture. It delivers significantly more performance than its

predecessors at a higher level of power efficiency.

The Arm®v8-A architecture brings a number of new features. These include 64-bit data processing, extended

virtual addressing and 64-bit general purpose registers. The A53 processor is Arm’s first Arm®v8-A processor

aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual-issue pipeline, and

improved integer, Arm® Neon™, Floating-Point Unit (FPU) and memory performance.

The A53 CPU supports two execution states: AArch32 and AArch64. The AArch64 state gives the A53 CPU its

ability to execute 64-bit applications, while the AArch32 state allows the processor to execute existing Arm®v7-A

applications.

For more information, see Arm Cortex-A53 Subsystem section in Processors and Accelerators chapter in the

device TRM.

8.2.2 Device/Power Manager

The WKUP_R5FSS is a single-core implementation of the Arm® Cortex®-R5F processor that acts as the

Device Manager responsible for boot, resource management, and power management functions. It also includes

accompanying memories (L1 caches and tightly-coupled memories), standard Arm® CoreSight™™ debug and

trace architecture, integrated vectored interrupt manager (VIM), ECC aggregators, and various other modules for

protocol conversion and address translation for easy integration into the SoC.

For more information, see Device Manager Cortex R5F Subsystem section in Processors and Accelerators

chapter in the device TRM.

8.2.3 MCU Arm Cortex-R5F Subsystem

The MCU_R5FSS is an Arm® Cortex®-R5F based subsystem that can run safety processing or be used as

a general purpose MCU. The processor includes 32KB instruction Cache, 32KB data cache, and 64KB Tightly

Coupled Memory.

For more information, see Cortex R5F Subsystem section in Processors and Accelerators chapter in the device

TRM.

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

www.ti.com

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AM62A7 датащи(PDF) 208 Page - Texas Instruments