 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
AM62A7 датащи(PDF) 170 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM62A7 датащи(HTML) 170 Page - Texas Instruments |
|
|
170 / 238 page  7.10.5.16.1 MMC0 - eMMC/SD/SDIO Interface MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the following eMMC applications: • Legacy SDR • High Speed SDR • HS200 MMC0 interface is also compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications: • Default Speed • High Speed • UHS–I SDR12 • UHS–I SDR25 • UHS–I SDR50 • UHS–I DDR50 • UHS–I SDR104 Table 7-79 presents the required DLL software configuration settings for MMC0 timing modes. Table 7-79. MMC0 DLL Delay Mapping for all Timing Modes REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG BIT FIELD [20] [15:12] [8] [4:0] [2:0] BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION Legacy SDR 8-bit PHY operating 1.8 V, 25 MHz 0x1 0x0 0x0 NA(1) 0x7 8-bit PHY operating 3.3 V, 25 MHz 0x1 0x0 0x0 NA(1) 0x7 High Speed SDR 8-bit PHY operating 1.8 V, 50 MHz 0x1 0x0 0x0 NA(1) 0x7 8-bit PHY operating 3.3 V, 50 MHz 0x1 0x0 0x0 NA(1) 0x7 HS200 8-bit PHY operating 1.8 V, 200 MHz 0x1 0x6 0x1 Tuning(2) 0x7 Default Speed 4-bit PHY operating 3.3 V, 25 MHz 0x1 0x0 0x1 0x0 0x7 High Speed 4-bit PHY operating 3.3 V, 50 MHz 0x1 0x0 0x1 0x0 0x7 UHS-I SDR12 4-bit PHY operating 1.8 V, 25 MHz 0x1 0xF 0x1 0x0 0x7 UHS-I SDR25 4-bit PHY operating 1.8 V, 50 MHz 0x1 0xF 0x1 0x0 0x7 UHS-I SDR50 4-bit PHY operating 1.8 V, 100 MHz 0x1 0xC 0x1 Tuning(2) 0x7 UHS-I DDR50 4-bit PHY operating 1.8 V, 50 MHz 0x1 0x9 0x1 Tuning(2) 0x7 UHS-I SDR104 4-bit PHY operating 1.8, V 200 MHz 0x1 0x6 0x1 Tuning(2) 0x7 (1) NA means Not Applicable (2) Tuning means this mode requires a tuning algorithm to be used for optimal input timing AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 www.ti.com 170 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
