AM62A7 datasheet(172/238 Pages) TI1

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7.10.5.16.1.1 Legacy SDR Mode

Table 7-81, Figure 7-67, Table 7-82, and Figure 7-68 present timing requirements and switching characteristics

for MMC0 – Legacy SDR Mode.

Table 7-81. MMC0 Timing Requirements – Legacy SDR Mode

see Figure 7-67

NO.

Operating

Voltage

MIN

MAX

UNIT

LSDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

1.8 V

4.2

3.3 V

2.15

LSDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

1.8 V

0.87

3.3 V

1.67

LSDR3

tsu(dV-clkH)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge

1.8 V

4.2

3.3 V

2.15

LSDR4

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

1.8 V

0.87

3.3 V

1.67

Figure 7-67. MMC0 – Legacy SDR – Receive Mode

Table 7-82. MMC0 Switching Characteristics – Legacy SDR Mode

see Figure 7-68

NO.

PARAMETER

Operating

Voltage

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

LSDR5

tc(clk)

Cycle time, MMC0_CLK

LSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

18.7

LSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

18.7

LSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

1.8 V

-2.1

2.1

3.3 V

-1.8

2.2

LSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

1.8 V

-2.1

2.1

3.3 V

-1.8

2.2

Figure 7-68. MMC0 – Legacy SDR – Transmit Mode

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

www.ti.com

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