AM62A7 datasheet(173/238 Pages) TI1

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7.10.5.16.1.2 High Speed SDR Mode

Table 7-83, Figure 7-69, Table 7-84, and Figure 7-70 present timing requirements and switching characteristics

for MMC0 – High Speed SDR Mode.

Table 7-83. MMC0 Timing Requirements – High Speed SDR Mode

see Figure 7-69

NO.

Operating

Voltage

MIN

MAX

UNIT

HSSDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

1.8 V

2.15

3.3 V

2.24

HSSDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

1.8 V

1.27

3.3 V

1.66

HSSDR3

tsu(dV-clkH)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge

1.8 V

2.15

3.3 V

2.24

HSSDR4

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

1.8 V

1.27

3.3 V

1.66

Figure 7-69. MMC0 – High Speed SDR Mode – Receive Mode

Table 7-84. MMC0 Switching Characteristics – High Speed SDR Mode

see Figure 7-70

NO.

PARAMETER

Operating

Voltage

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSSDR5

tc(clk)

Cycle time, MMC0_CLK

HSSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

1.8 V

-1.55

3.05

3.3 V

-1.8

2.2

HSSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

1.8 V

-1.55

3.05

3.3 V

-1.8

2.2

Figure 7-70. MMC0 – High Speed SDR Mode – Transmit Mode

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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