AM62A7 datasheet(167/238 Pages) TI1

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7.10.5.15.2 MCSPI — Peripheral Mode

Table 7-77, Figure 7-65, Table 7-78, and Figure 7-66 present timing requirements and switching characteristics

for SPI – Peripheral Mode.

Table 7-77. MCSPI Timing Requirements – Peripheral Mode

see Figure 7-65

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SS1

tc(SPICLK)

Cycle time, SPIn_CLK

SS2

tw(SPICLKL)

Pulse duration, SPIn_CLK low

0.45P

(1)

SS3

tw(SPICLKH)

Pulse duration, SPIn_CLK high

0.45P

(1)

SS4

tsu(PICO-SPICLK)

Setup time, SPIn_D[x] valid before SPIn_CLK active edge

SS5

th(SPICLK-PICO)

Hold time, SPIn_D[x] valid after SPIn_CLK active edge

SS8

tsu(CS-SPICLK)

Setup time, SPIn_CSi valid before SPIn_CLK first edge

SS9

th(SPICLK-CS)

Hold time, SPIn_CSi valid after SPIn_CLK last edge

(1)

P = SPIn_CLK period in ns.

SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

SPI_CS[i]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

POL=0

POL=1

PHA=1

EPOL=1

SS3

SS1

SS3

SS1

SS3

SS1

SS2

SS1

SS8

SS9

SS8

SS9

SS2

SS3

SS2

SS4

SS5

SS4

SS5

SS4

SS5

SPRSP08_TIMING_McSPI_04

Figure 7-65. SPI Peripheral Mode Receive Timing

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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