AD4697 datasheet(30/107 Pages) AD

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Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 30 of 107

ANALOG INPUTS

Figure 66 shows an equivalent circuit of the AD4697/AD4698 ana-

log inputs (IN0 to IN7 and COM).

Figure 66. Equivalent Analog Input Circuit

A low crosstalk analog multiplexer routes the signals from the

analog input pins to the ADC core inputs. The impedance of the

analog inputs is modeled as the parallel combination of the pin ca-

pacitance (CPIN) and the network formed by the series connection

of RIN and CDAC. RIN represents the ADC input series resistance

and the multiplexer switch resistance and is typically 240 Ω. CDAC

represents the ADC sampling capacitive DAC shown in Figure 63

and is typically 60 pF.

Each analog input has a unique overvoltage protection clamp

circuit, represented by OV CLAMP in Figure 66. The clamps protect

the analog inputs from dc overvoltage conditions and eliminate

the need for additional external protection diodes. See the Input

Overvoltage Protection Clamps section for a detailed description of

the overvoltage protection clamps.

REXT and CEXT in Figure 66 represent an external, RC low-pass

filter, which is included in the system design to limit the bandwidth

of the input signal. REXT can also be used to improve overvoltage

protection of the analog inputs. See the External RC Filter section

for detailed descriptions of the REXT and CEXT functions.

Multiplexer

The AD4697/AD4698 contain a flexible, low crosstalk analog mul-

tiplexer for selecting from the eight analog inputs and internal

temperature sensor and routing them to the inputs of the 16-bit,

pseudo differential SAR, ADC core. Figure 67 shows a simplified

schematic of the internal multiplexer. The SWMUX+ and SWMUX−

switches shown in Figure 63 and Figure 67 represent the multiplex-

er switches that route the selected channel to the ADC inputs

(labeled ADCIN+ and ADCIN− in Figure 63). SWMUX+ and SWMUX−

are break-before-make and are controlled by the internal channel

sequencing logic (see the Channel Sequencing Modes section).

The multiplexer allows flexible analog input channel configuration.

The SWMUX− position is user programmable and can be assigned to

any of the pins shown in Figure 67 (see the Channel Configuration

Options section).

Figure 67. Multiplexer Simplified Schematic

Channel Configuration Options

The AD4697/AD4698 feature several channel configuration options

that allow the device to interface with a variety of signals. The

channel configuration can be independently programmed for each

of the eight analog inputs (IN0 through IN7).

The channel configuration settings include pin pairing assignments

and signal polarity modes. The pin pairing options assign the

position of SWMUX− for each position of SWMUX+ and determine

which signal is routed to the negative side of the SAR ADC core

(ADCIN− in Figure 63). The signal polarity modes configure the

ADCIN− voltage range. Figure 68 shows the pin pairing and voltage

ranges for the different channel configuration options.

The pin pairing assignment options include the following:

►

Figure 68, IN0 to IN7 paired with REFGND

►

Figure 69, IN0 to IN7 paired with COM

►

Figure 70, even numbered input paired with the next highest odd

numbered input (for example, IN0 with IN1, IN2 with IN3, and so

on).

The two signal polarity modes are called unipolar mode and pseu-

dobipolar mode. When a channel is in unipolar mode, the signal

routed to ADCIN− is nominally 0 V (relative to REFGND). When

a channel is in pseudobipolar mode, the signal routed to ADCIN−

is nominally VREF/2 V (relative to REFGND). The valid operating

input voltage specification for unipolar and pseudobipolar modes

are shown in Table 1.

When an input is configured in unipolar mode, its output codes are

in straight binary format. When an input is configured in pseudobi-

polar mode, its output codes are in twos complement format. See

the Transfer Function section for an example of the output code

formatting for both unipolar and pseudobipolar modes.

The pin pairing assignments are selected with the IN_PAIR bit

field in the CONFIG_INn registers. The signal polarity modes are

selected with the IN_MODE bit in the CONFIG_INn registers.

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