AD4697 datasheet(9/107 Pages) AD

9 / 107 page

Data Sheet

AD4697/AD4698

SPECIFICATIONS

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Rev. 0 | 9 of 107

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

fS = 500 kSPS, REFIN = 4.096 V

18.3

22.5

fS = 1 MSPS, REFIN = 4.096 V

34.1

42.6

Autocycle Mode Power Dissipation

LDO_IN = 5 V, internal LDO enabled, autocycle mode

enabled

AC_CYC = 0x0

2.3

AC_CYC = 0x7

0.2

TEMPERATURE RANGE

Specified Performance

TMIN to TMAX

−40

+125

°C

1 See the Channel Configuration Options section for a detailed description of unipolar mode, pseudobipolar mode, and the channel pin assignment options.

2 IN+ and IN− represent the analog inputs connected to the positive and negative inputs of the AD4697/AD4698 ADC core via the internal multiplexer (see the Multiplexer

section and Channel Configuration Options section).

3 The analog input leakage current specification refers to the input current of the analog input pins during periods when the ADC is not performing conversions and the

analog input voltage is already settled.

4 Offset error and gain error specifications are taken with the offset and gain correction registers set to the default values, which correspond to no offset or gain correction.

See the Offset and Gain Correction section for more information.

5 %FS is the percentage of the ADC full scale (see the Transfer Function section for a definition of full scale).

6 The REFIN pin and internal reference buffer are only available on the WLCSP model of the AD4698 . All specifications and conditions regarding REFIN or the internal

reference buffer are therefore only relevant for WLCSP model.

7 The reference buffer turn-on time specification refers to the amount of time between the reference buffer being enabled and the REF voltage settling to 0.01% accuracy

(see the Internal Reference Buffer section).

8 REXT and CEXT refer to the resistor and capacitor, respectively, that make up the recommended external RC filters at the analog inputs (see the External RC Filter section).

9 For the power supply current and power dissipation specifications where analog input high-Z mode is enabled, analog input high-Z mode is set to be enabled for all

channels. The power consumption scales with the percentage of conversions performed with analog input high-Z mode enabled.

TIMING SPECIFICATIONS

AVDD = 3.15 V to 5.5 V, LDO_IN = 2.4 V to 5.5 V with internal LDO enabled, LDO_IN = AGND with internal LDO disabled, VDD = 1.71 V to

1.89 V with internal LDO disabled, VIO = 1.14 V to 1.98 V, AGND = REFGND = IOGND = 0 V, VREF = 2.4 V to 5.1 V, fS = 1 MSPS for the

AD4698, fS = 500 kSPS for the AD4697, digital output load capacitance = 20 pF, autocycle mode disabled, no active overvoltage protection

clamps, and TA = −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter1

Symbol

Min

Typ

Max

Unit

Conversion Time

tCONVERT

380

415

Acquisition Time

tACQ

Two-Cycle Command Mode, Standard Sequencer, or Advanced Sequencer Enabled

fS = 1 MSPS

715

fS = 500 kSPS

1715

Single-Cycle Command Mode2 Enabled

CNV Period (Time Between Conversions)

tCYC

fS = 1 MSPS, Autocycle Mode Disabled

1000

fS = 500 kSPS, Autocycle Mode Disabled

2000

Autocycle Mode Enabled

AC_CYC = 0x0

8.5

11.5

μs

AC_CYC = 0x1

μs

AC_CYC = 0x2

μs

AC_CYC = 0x3

μs

AC_CYC = 0x4

100

115

μs

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