AD4697 datasheet(28/107 Pages) AD

28 / 107 page

Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 28 of 107

TRANSFER FUNCTION

Figure 64 shows the AD4697/AD4698 data processing path. The

SAR ADC core generates one 16-bit output code per conversion

period. The OSR setting for the selected analog input channel

determines how many consecutive 16-bit output code results are

averaged, and then the offset and gain correction settings are

applied to generate the final result to be read over the SPI in

conversion mode (see the Oversampling and Decimation section

and the Offset and Gain Correction section).

The conversion result length is determined by the OSR setting.

The conversion result resolution can range from 16 bits to 19 bits

for an OSR of 1 and 64, respectively (see the Oversampling and

Decimation section).

The conversion result encoding format is determined by the se-

lected polarity mode. The results are in straight binary format

for channels configured in unipolar mode, and twos complement

for channels configured in pseudobipolar mode (see the Channel

Configuration Options section).

The AD4697/AD4698 include offset and gain correction for each

channel that can be configured to compensate for first-order system

errors. The offset and gain correction registers modify the ADC

transfer function digitally (see the Offset and Gain Correction sec-

tion).

The ideal transfer function is shown in Figure 65. The Converting

Between Codes and Volts section describes the relationship be-

tween output codes and input voltages vs. VREF, OSR, polarity

modes, and offset and gain correction settings. Table 9 through

Table 12 show examples of different voltage inputs and the corre-

sponding results for each OSR and polarity mode option (assuming

an ideal ADC transfer function and with the offset and gain correc-

tion values set to default values).

Figure 64. ADC Data Processing Path

Figure 65. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

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