AD4697 datasheet(40/107 Pages) AD

40 / 107 page

Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 40 of 107

BUSY INDICATOR

The busy indicator acts as a data ready signal that can be used

to trigger an interrupt service routine on the digital host to initiate

an SPI transaction to read the ADC result (see the Conversion

Mode section and SPI Peripheral Synchronization in Conversion

Mode section). The busy indicator can be enabled on the serial

data outputs and on some of the general-purpose pins.

Busy Indicator on Serial Data Outputs

When the busy indicator is enabled on the serial data outputs, the

serial data outputs are high impedance while the ADC is in the

conversion phase, and transition low when the ADC result is ready.

Set the SDO_STATE bit in the setup register to 1 to enable the busy

indicator on the serial data outputs.

Figure 94 through Figure 99 show the relative timing of the CNV

rising edges to the busy indicator on the serial data outputs.

The serial data output mode selected by the SDO_MODE bit field

determines which pins are assigned as the serial data outputs

(see the Serial Data Output Modes section). When SDO_STATE

is set to 1, the busy indicator is enabled on all pins assigned

as serial data outputs. When single-SDO mode is selected, the

busy indicator is only output on SDO. When dual-SDO mode or

quad-SDO mode is selected, the busy indicator is also output on

the relevant general-purpose pins as indicated in Table 19.

When enabling the busy indicator on the serial data outputs, place

pull-up resistors (2 kΩ minimum) on each utilized pin to ensure that

the serial data output lines are pulled high until the ADC result is

ready.

The serial data outputs are forced to a high impedance state

whenever the CS pin is driven high. If the CS pin is high when the

ADC result is ready, the serial data outputs remain high impedance

until the CS pin is brought low (see the Digital Interface section).

Busy Indicator on General-Purpose Pins

When the busy indicator is enabled on a general-purpose pin, the

selected general-purpose pin is driven high while the ADC is in

the conversion phase, and transitions low when the ADC result is

ready. Set the BUSY_GP_EN bit in the GP_MODE register to 1 to

enable the busy indicator on the selected general-purpose pin.

Figure 94 through Figure 99 show the relative timing of CNV rising

edges to the busy indicator rising and falling edges.

On the WLCSP option of the AD4698, the busy indicator can be

enabled on either the BSY_ALT_GP0 pin or the GP3 pin. The

BUSY_GP_SEL bit in the GP_MODE register selects which of the

general-purpose pins are configured as the busy indicator. Set the

BUSY_GP_EN bit in the GP_MODE register to 1 to enable the busy

indicator on the selected general-purpose pin.

On the LFCSP option of the AD4697/AD4698, the busy indicator

can be enabled only on the BSY_ALT_GP0 pin, and the state of

the BUSY_GP_SEL bit has no impact on device behavior. Set the

BUSY_GP_EN bit in the GP_MODE register to 1 to enable the busy

indicator on the BSY_ALT_GP0 pin.

When a general-purpose pin is assigned as the busy indicator, it is

not forced to high impedance when the CS pin is high, which allows

the digital host to leave the serial interface completely disabled until

a busy indicator falling edge is registered (see the SPI Peripheral

Synchronization in Conversion Mode section).

The BSY_ALT_GP0 and GP3 pins can also be configured to per-

form other functions than the busy indicator, and all other higher

priority functions must be disabled to configure these functions as

the busy indicator. See the General-Purpose Pins section for details

on configuring the general-purpose pins.

CHANNEL SEQUENCING MODES

In conversion mode, the AD4697/AD4698 multiplexer channel up-

dates once per conversion period at the start of the ADC core

acquisition phase, as described in the Converter Operation section.

The multiplexer is controlled by internal channel sequencing logic,

and there are four options for programming the channel sequence.

The standard sequencer and advanced sequencer automates pro-

gression through a preprogrammed channel sequence. When either

the standard sequencer or advanced sequencer is enabled, the dig-

ital host is not required to provide channel sequencing instructions

while reading conversion results over the SPI, which reduces the

digital resource requirements.

Two-cycle command mode and single-cycle command mode allow

the digital host to directly control the channel sequence via 5-bit

commands written over the serial interface during conversion data

readback frames. Two-cycle command mode and single-cycle com-

mand mode enable systems with dynamic and adaptive channel

sequencing requirements, such as control loop applications.

Figure 76 through Figure 80 show conversion mode example timing

diagrams of the AD4697/AD4698 multiplexer channel selection,

ADC sampling, and conversion data output relative to the channel

sequencing settings and the CNV signal. The BUSY signal refers

to the busy indicator, which can be enabled on the BSY_ALT_GP0

pin, the GP3 pin, or the serial data outputs, as described in the

Busy Indicator section. The SDOx signal refers to the SDO pin

plus the addition serial data output signals if dual-SDO mode or

quad-SDO mode is enabled, as described in the Serial Data Output

Modes section.

Table 15 lists the configuration settings used to select from the four

channel sequencing modes. Both the STD_SEQ_EN bit and the

NUM_SLOTS_AS bit field are located in the SEQ_CTRL register.

The CYC_CTRL bit is located in the setup register.

As noted in the Channel Configuration Options section, when even

and odd numbered inputs are paired, selecting the odd numbered

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