AD4697 datasheet(94/107 Pages) AD

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Data Sheet

AD4697/AD4698

analog.com

Rev. 0 | 94 of 107

Table 40. Bit Descriptions for SPI_STATUS

Bits

Bit Name

Description

Reset

Access

ADDR_INVALID

Invalid Address Error Flag. This bit is set to 1 when an SPI transaction attempts to access a nonexistent register

(a register with an address outside of the specified range of values in Table 31).

0x0

R/W1C

Device Status Register

Address: 0x0014, Reset: 0x20, Name: Status

Table 41. Bit Descriptions for Status

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

COM_CLAMP_FLAG

COM Overvoltage Clamp Flag. This bit indicates if the COM overvoltage protection clamp is active because

of an overvoltage event. This bit is not sticky and is cleared when the COM overvoltage protection clamp is

inactive.

0x0

0: COM overvoltage protection clamp inactive.

1: COM overvoltage protection clamp active.

RESET_FLAG

Reset Flag. This bit indicates whether a hardware reset or software reset occurred since the last time this bit was

read (see the Device Reset section). This bit is automatically cleared when read.

0x1

0: no device reset occurred since this bit was last read.

1: a device reset occurred since this bit was last read.

RESERVED

Reserved.

0x0

TD_ALERT

Threshold Detection Alert Indicator. This bit indicates if any combination of the upper or lower alert indicators for

IN0 to IN7 is asserted. This bit is the logical OR of all HI_INn and LO_INn bits in the ALERT_STATUS1 register

and the ALERT_STATUS2 register. This bit is not sticky.

0x0

0: no upper or lower alert indicators asserted.

1: at least one upper or lower alert indicator asserted.

SPI_ERROR

General Interface Error Flag. This bit indicates if any of the error flags in the SPI_STATUS register are asserted.

This bit is the bitwise logical OR of all bits in the SPI_STATUS register.

0x0

0: no interface error detected.

1: one or more interface errors detected.

CLAMP_FLAG

General Overvoltage Protection Clamp Flag. This bit indicates if any IN0 to IN7 overvoltage protection clamps

were activated by an overvoltage event (if any of the INX_CLAMP_FLAG bits are asserted). This bit is sticky and

is only cleared if all INX_CLAMP_FLAG bits are deasserted when the bit is read.

0x0

0: all IN0 to IN7 overvoltage clamps are inactive.

1: at least one IN0 to IN7 overvoltage clamps are active.

RESERVED

Reserved.

0x0

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