AD4697 datasheet(84/107 Pages) AD

84 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 84 of 107

Table 28. Minimum fSCK Requirements vs. Sample Rate and Serial Data Output Modes (OSR = 1)

Sample Rate (kSPS)

Status Bits1

Single-SDO Mode

Dual-SDO Mode

Quad-SDO Mode

1000 (AD4698 Only)

Disabled

32 MHz

16 MHz

8 MHz

1000 (AD4698 Only)

Enabled

48 MHz

24 MHz

12 MHz

500

Disabled

11 MHz

5.5 MHz

2.75 MHz

500

Enabled

16 MHz

8 MHz

4 MHz

100

Disabled

2 MHz

1 MHz

500 kHz

100

Enabled

2.6 MHz

1.3 MHz

650 kHz

1 In the calculations in Table 28, NBITS = 16 when status bits are disabled and NBITS = 24 when status bits are enabled.

RESET Connection Recommendations

The RESET input allows the digital host to trigger a full device reset

with a GPIO (see the Hardware Reset section). The RESET input is

active low and must be driven low to initiate a hardware reset. The

AD4697/AD4698 remain in the reset state until the RESET input is

driven high.

Hardware resets are not required to operate the AD4697/AD4698

because the SPI provides a software reset option (see the Software

Reset section). For systems not utilizing hardware reset functionali-

ty, tie the RESET input to VIO to ensure it is pulled high during

device operation.

To utilize hardware resets, connect the RESET input to a GPIO

or equivalent digital output from the digital host. The signal driving

RESET must idle high. It is recommended to also include a weak

pull-up resistor to VIO on the RESET input to ensure it is pulled

high until the digital host output is in a defined state. The host firm-

ware function for performing hardware resets must pulse RESET

low following the timing requirements in Figure 104.

DEVICE CONFIGURATION

RECOMMENDATIONS

The following are recommendations for configuring the desired

AD4697/AD4698 features and settings via the configuration regis-

ters described in the Register Information section.

The AD4697/AD4698 must be in register configuration mode to ac-

cess the configuration registers via the SPI. The AD4697/AD4698

enter register configuration mode on device power-up and following

device resets. The settings in the configuration registers must be

properly programmed for the specific application prior to entering

conversion mode and performing conversions.

On device power-up, it is recommended to perform either a hard-

ware or software reset as described in the Device Reset section.

First, program the contents of the SPI_CONFIG_A, SPI_CON-

FIG_B, and SPI_CONFIG_C registers to the desired settings to

ensure the AD4697/AD4698 SPI protocol is configured to be com-

patible with the digital host (see the Register Configuration Mode

section). The scratch pad register (SCRATCH_PAD) allows the

digital host to validate communications with the AD4697/AD4698 by

writing test values and reading them back without affecting device

settings.

When using the internal reference buffer (WLCSP only), it is recom-

mended to configure the REF_CTRL register contents as soon as

possible to give ample time for the output of the internal reference

buffer to settle while configuring the remaining registers (as descri-

bed in the Optimizing Reference Buffer Startup section). When

not using the internal reference buffer, the timing for updating the

REF_CTRL register is not important, but the REF_CTRL register

must be updated before entering conversion mode if the required

reference input high-Z mode enable setting, VREF_SET setting, or

overvoltage reduced current mode setting are different from their

default settings (see Table 46).

Next, when powering VDD externally, it is recommended to disable

the internal LDO by setting the LDO_EN bit in the setup register to

0 (see the Internal LDO section). Note that setting the SPI_MODE

bit to a 1 puts the AD4697/AD4698 into conversion mode. Ensure

that SPI_MODE is set to 0 until the remaining configuration regis-

ters are properly configured.

Next, configure the channel sequencing registers for the desired

channel sequencing mode. The SEQ_CTRL register contains the

STD_SEQ_EN bit and NUM_SLOTS_AS bit field, which must be

configured to select the desired channel sequencing mode. By de-

fault, the STD_SEQ_EN bit is set to 1, which selects the standard

sequencer (see Table 47).

If using the standard sequencer, ensure the STD_SEQ_EN bit is

set to 1, and then program the STD_SEQ_CONFIG register and

TEMP_CTRL register to select the channels for the sequence (see

Table 49 and Table 53).

If using the advanced sequencer, update the SEQ_CTRL register

to set the STD_SEQ_EN bit to 0 and set the NUM_SLOTS_AS

bit field to the desired number of advanced sequencer slots, and

program the appropriate number of AS_SLOTn registers and the

TEMP_CTRL register to implement the desired channel sequence

(see Table 60 and Table 53).

If using either two-cycle command mode or single-cycle command

mode, update the SEQ_CTRL register to set the STD_SEQ_EN

bit to 0 but keep the NUM_SLOTS_AS bit field set to 0x0. The

CYC_CTRL bit must also be set to select between two-cycle and

AD4697 датащи(PDF) 84 Page - Analog Devices

AD4697 датащи(HTML) 84 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL