AD4697 datasheet(73/107 Pages) AD

73 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

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Rev. 0 | 73 of 107

ANALOG INPUT OVERVOLTAGE PROTECTION

The external resistor in the external RC filter (represented by REXT

in Figure 66, Figure 112, and Figure 115) works with the input

overvoltage protection clamps to provide overvoltage protection to

the analog inputs (see the Input Overvoltage Protection Clamps

section).

An overvoltage event is defined as an event where the overvoltage

protection clamps are activated as a result of the input voltage

on IN0 to IN7 or COM exceeding the clamp activation voltage

specification (VACT in Figure 115). The maximum VACT voltage

specification is VREF + 0.55 V (see Table 1).

When activated, the clamp on the given channel sinks current

from the source to ground (see ICLAMP in Figure 115), resulting

in a voltage drop across REXT. The AD4697/AD4698 overvoltage

protection clamps support a maximum sustained ICLAMP current of

5 mA (see Table 1). REXT therefore isolates the analog input pin

voltage from the applied voltage (VIN). The maximum VIN that can

be supported for a given analog input is a function of VREF and

REXT. The following relation gives the required value of REXT to limit

the clamp current to the maximum supported current

(5 mA) given the VREF and maximum expected VIN:

REXT=VIN,MAX−VREF

5 mA

(14)

For example, if the analog input source can swing to 7.5 V and

VREF = 5 V, REXT must be approximately 500 Ω to limit the

clamp current to 5 mA. If this resistor is being sized based upon

the clamping current limits, CEXT must be carefully chosen to

ensure adequate that input bandwidth is achieved (see the Analog

Front-End Noise Considerations and Signal Settling Requirements

sections for more information).

The REXT value also must be selected to ensure stability of the

overvoltage protection clamp circuit, if desired. See the Overvoltage

Protection Clamp Stability section for more information.

Figure 115. Analog Input Overvoltage Event

REFERENCE CIRCUITRY DESIGN

The AD4697/AD4698 VREF sets the full-scale range of the ADC

core and determines the resulting output code for a given analog

input voltage (see the Transfer Function section). The VREF voltage

therefore has a direct impact on the overall system accuracy and

ac performance. The reference companion circuitry for the AD4697/

AD4698 must have adequate noise performance, accuracy, drift,

and signal settling characteristics for the end application.

The REF input is a dynamic current load that pulls charge from the

reference circuitry during the conversion phase of the ADC core,

and the reference circuit must be able to maintain a stable VREF

while the ADC is performing conversions to maintain performance

(that is, gain error).

The AD4697/AD4698 reference input high-Z mode significantly

reduces the magnitude of the average current of the REF input

when enabled. The WLCSP option of the AD4698 also includes

an optional internal reference buffer to provide a true buffered high-

impedance reference input. The reference input high-Z mode and

internal reference buffer significantly reduce the drive requirements

of the reference circuitry, allowing system designers to prioritize dc

accuracy, power, and system footprint targets.

Figure 116 shows the typical connection diagram for the AD4697/

AD4698 companion reference circuit. The reference circuitry con-

sists of a voltage reference, CREF, and any accompanying refer-

ence buffer or analog low-pass filtering. A reference buffer is

required if the selected voltage reference does not have an ade-

quate load regulation to drive the REF input at the desired ADC

sample rate (see the Reference Circuit Design for Driving REF

Input section).

CREF supplies the charge necessary for the ADC core to perform

the bit trials as part of the conversion phase and filters noise from

the other reference circuitry. CREF must be sufficiently large to pre-

vent deviations in VREF during the ADC bit trials. When reference

input high-Z mode is enabled, the amount of charge pulled by the

REF input is significantly reduced, thereby reducing the minimum

CREF capacitance. When reference input high-Z mode is disabled,

a 10 µF CREF is recommended. When reference input high-Z mode

is enabled, a 1 µF CREF is recommended. CREF is required whether

reference input high-Z mode or the internal reference buffer are

enabled or disabled.

The PCB layout of the reference circuitry relative to the AD4697/

AD4698 REF input is critical to ensuring optimal performance. The

Layout Guidelines section provides recommendations and guide-

lines for the layout of the reference circuit components.

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