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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD4697 датащи(PDF) 89 Page - Analog Devices |
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AD4697 датащи(HTML) 89 Page - Analog Devices |
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89 / 107 page  Data Sheet AD4697/AD4698 REGISTER INFORMATION analog.com Rev. 0 | 89 of 107 REGISTER OVERVIEW The AD4697/AD4698 have programmable configuration registers that contain the bits and fields used to monitor device status and configure the device. Reading or writing to these bits and fields requires reading or writing to the registers that contain them. The AD4697/AD4698 SPI is used to read and write to the configuration registers (see the Register Configuration Mode section). The AD4697/AD4698 register map memory space is divided into bytes. Each byte of memory has a unique address, ranging from 0x0000 to 0x017F. Table 31 shows the register memory address assignments for all of the AD4697/AD4698 configuration registers. Each configuration register is a single byte or multiple bytes in length. Registers that are multiple bytes long are called multibyte registers. The address of each multibyte register is defined as the address of its least significant byte, but each byte in a multibyte register has a unique address in the register map memory space. For example, the STD_SEQ_CONFIG register is two bytes long, and its least significant byte address is 0x0024 and its most signifi- cant byte address is 0x0025. The state of the MB_STRICT bit in the SPI_CONFIG_C register determines whether all bytes in a mul- tibyte register must be read or written in a single SPI transaction, or if each individual byte must be read or written in separate SPI transactions (see the Multibyte Register Access section). Bits and fields in the AD4697/AD4698 configuration registers are defined as read only, read/write, or write 1 to clear bits (R/W1C). Read only bits can only be read from and cannot be updated by SPI writes from the host SPI. Read/write bits can be read from or written to. R/W1C can be read from and are only reset to 0 when the digital host writes a 1 in their memory location. In the access column of Table 31, registers that contain exclusively read only bits are represented with R and registers with writeable bits are represented with R/W. In the access column of Table 32 through Table 60, read only bits are represented with R, read/write bits are represented with R/W, and write 1 to clear bits are represented with R/W1C. The SPI_STATUS register contains various error flags that indicate whether a SPI read or write transaction violated one of several as- pects of the protocols outlined in the Register Configuration Mode section (see Table 40). The SPI_ERROR bit in the status register is the bitwise logical OR of the error flags in the SPI_STATUS register (see Table 41). Table 31. Configuration Register Names and Descriptions Address Name Description Length Reset Access 0x0000 SPI_CONFIG_A Interface Configuration A Single byte 0x10 R/W 0x0001 SPI_CONFIG_B Interface Configuration B Single byte 0x00 R/W 0x0003 DEVICE_TYPE Device type Single byte 0x07 R 0x000A SCRATCH_PAD Scratch pad Single byte 0x00 R/W 0x000C VENDOR_L Vendor ID (lower byte) Single byte 0x56 R 0x000D VENDOR_H Vendor ID (upper byte) Single byte 0x04 R 0x000E LOOP_MODE Loop mode Single byte 0x00 R/W 0x0010 SPI_CONFIG_C Interface Configuration C Single byte 0x23 R/W 0x0011 SPI_STATUS Interface status Single byte 0x00 R/W 0x0014 Status Device status Single byte 0x20 R 0x0015 ALERT_STATUS1 Alert status (IN0 to IN3) Single byte 0x00 R 0x0016 ALERT_STATUS2 Alert status (IN4 to IN7) Single byte 0x00 R 0x001A CLAMP_STATUS Clamp status Single byte 0x00 R 0x0020 Setup Device setup Single byte 0x10 R/W 0x0021 REF_CTRL Reference control Single byte 0x12 R/W 0x0022 SEQ_CTRL Sequencer control Single byte 0x80 R/W 0x0023 AC_CTRL Autocycle control Single byte 0x00 R/W 0x0024 STD_SEQ_CONFIG Standard sequencer configuration Multibyte 0x0001 R/W 0x0026 GPIO_CTRL GPIO enable Single byte 0x00 R/W 0x0027 GP_MODE General-purpose pin function control Single byte 0x00 R/W 0x0028 GPIO_STATE GPIO state Single byte 0x00 R/W 0x0029 TEMP_CTRL Temperature sensor control Single byte 0x00 R/W 0x0030 to 0x0037 CONFIG_INn Analog input settings configuration Single byte 0x08 R/W 0x0040 to 0x004E UPPER_INn Upper threshold value Multibyte 0x07FF R/W 0x0060 to 0x006E LOWER_INn Lower threshold value Multibyte 0x0000 R/W 0x0080 to 0x008E HYST_INn Hysteresis setting Multibyte 0x0010 R/W 0x00A0 to 0x00AE OFFSET_INn INn offset correction Multibyte 0x0000 R/W |
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