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AD4697 датащи(PDF) 52 Page - Analog Devices |
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AD4697 датащи(HTML) 52 Page - Analog Devices |
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52 / 107 page ![]() Data Sheet AD4697/AD4698 DIGITAL INTERFACE analog.com Rev. 0 | 52 of 107 CONVERSION MODE When the AD4697/AD4698 are in conversion mode, CNV rising edges initiate conversions on the selected channel, and the chan- nel sequencing logic updates the multiplexer to the next channel (see the Converter Operation and Channel Sequencing Modes sec- tions). The device enters conversion mode when the SPI_MODE bit in the setup register is set to 1. In conversion mode, the SPI is used to read the ADC results and write the 5-bit SDI commands shown in Table 18. Figure 94 to Figure 101 show timing diagrams for SPI frames relative to performing conversions. The CNV signal and the CS pin can be tied together to enable interfacing with a single 4-wire SPI port (see Figure 101). Each ADC result is available until the next CNV rising edge occurs. An optional set of five status bits can be appended to the ADC data. The status bits include channel information, the overvoltage clamp flag, and a threshold detection alert indicator. See the Status Bits section for a description of the status bits and how they are enabled. In conversion mode, the general-purpose pins can be assigned as an additional serial data output to reduce the SCK frequency required to shift out the ADC result plus optional status bits before the next conversion occurs. See the Serial Data Output Modes section for a description of the options available on both package options of the AD4697/AD4698 and how to enable these modes. The general-purpose pins can also be assigned as either the busy indicator or the threshold detection alert indicator. Figure 94 to Figure 101 show the relative timing of the CNV signal and the busy and alert indicators when they are assigned to the general-purpose pins. The General-Purpose Pins section describes how to set the general-purpose pins to the desired function. When autocycle mode is enabled, the AD4697/AD4698 generate their own internal convert start signal to autonomously perform conversions without a CNV signal from the digital host (see the Autocycle Mode section). Status Bits A set of five status bits can be appended to the end of each conversion result. The status bits allow the digital host to monitor the status of the analog inputs without interrupting analog-to-digital conversions. Table 17 shows the names and descriptions of the status bits. By default, the OV_ALT status bit indicates the status of the over- voltage clamp flags (the bitwise logical OR of the CLAMP_FLAG bit and COM_CLAMP_FLAG bit in the status register). When the OV_ALT_MODE bit in the GP_MODE register is set to 1, the OV_ALT status bit is the logical OR of the CLAMP_FLAG bit and the threshold detection alert indicator (TD_ALERT bit in the status register). The digital host can monitor the state of the OV_ALT bit to detect and respond to out of range events. The INX bits indicate which of the eight analog inputs the conver- sion result corresponds to. The values for the INX bits range from 0 to 7 (0x0 to 0x7) and correspond to IN0 to IN7, respectively. An INX value of 15 corresponds to the temperature sensor. The INX bits can be used by the digital host to align the ADC data with the sequence of analog input channels. Set the STATUS_EN bit in the setup register to 1 to enable the status bits. The status bits are disabled by default. When the status bits are enabled, the serial data output word extends to 24 bits, where Bit 20 to Bit 24 contain the status bits (see Table 21, Table 22 and Table 23). Table 17. Status Bits Names and Descriptions Status Word Index Bit Name Description Bit 4 OV_ALT Active high. Indicates the status of the overvoltage protection clamp flag and (if enabled) the status of the threshold detection alert indicator. Bits[3:0] INX Indicates what analog input channel the ADC data corresponds to (IN0 to IN7). Table 18. Conversion Mode Commands Channel Sequencing Mode 5-Bit SDI Command (CMD) Description Two-Cycle Command Mode and Single-Cycle Command Mode 0x00 to 0x09, 0x0B to 0x0E NOOP 0x0A Register configuration mode command 0x0F Temperature sensor channel selection 0x10 to 0x17 and 0x18 to 0x1F IN0 to IN7 channel selection Standard Sequencer and Advanced Sequencer 0x00 to 0x09, 0x0B to 0x1F NOOP 0x0A Register configuration mode command |
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