AD4697 datasheet(65/107 Pages) AD

65 / 107 page

Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 65 of 107

GPIO

Each general-purpose pin can be configured as a GPIO using

the GPIn_EN and GPOn_EN bits in the GPIO_CTRL register,

respectively (see Table 50). A general-purpose pin is configured as

an input when its corresponding GPIn_EN bit is set to 1 and is

configured as an output when its corresponding GPOn_EN bit is set

to 1.

The AD4697/AD4698 GPIO functionality allows the digital host to

control logic inputs or monitor logic outputs of other devices in the

system with the AD4697/AD4698 SPI instead of using additional

digital host GPIO pins. The GPIO functionality is especially useful

in digitally isolated applications because the functions reduce the

number of required digital isolation channels.

When a general-purpose pin is configured as a general-purpose

input, it can be connected to a logic output of another device in

the system, and the digital host can read the GPIO_STATE register

to monitor its state. The GPI_READ bit field in the GPIO_STATE

Table 52). The logic input thresholds for the general-purpose inputs

are specified in Table 1 as VIL and VIH.

When a general-purpose pin is configured as a general-purpose

output, it can be connected to a logic input of another device in

the system, such as other multiplexers or programmable gain am-

plifiers, and the digital host can write to the GPIO_STATE register

to set the state of this signal. The GPO_WRITE bit field in the

GPIO_STATE register controls the state of the general-purpose

outputs (see Table 52). The logic output thresholds for the general-

purpose outputs are specified in Table 1 as VOL and VOH.

Because the LFCSP option does not have the GP1, GP2, or GP3

pins, the corresponding GPI_READ bits are hard-coded to 0, and

writing to the corresponding GPO_WRITE bits have no effect.

DEVICE RESET

A device reset reinitializes the AD4697/AD4698 configuration regis-

ters. The AD4697/AD4698 provide several options for performing

a device reset, including a hardware reset, a software reset, and

PORs.

Hardware resets, software resets, and PORs all assert the RE-

SET_FLAG bit in the status register. The RESET_FLAG bit is a

read to clear bit and is automatically set to 0 after a valid read from

the status register. The RESET_FLAG bit can be used by the digital

host to confirm that the device has executed a device reset, or if a

reset was performed unintentionally.

All device reset methods require a delay between the start of the

reset instruction and when the AD4697/AD4698 SPI is ready to

receive communications from the digital host. The device reset

delays are shown in Figure 104 through Figure 111 and in

Table 2. When the digital host attempts to perform an SPI read or

write transaction before the device is ready, the transaction is con-

sidered invalid, and the NOT_RDY_ERROR bit in the SPI_STATUS

is only reset when set to 1 with a valid register write transaction.

Hardware Reset

A hardware reset is initiated by the RESET falling edge. Figure 104

shows a timing diagram for performing a hardware reset. tRESETL

is the minimum amount of time that RESET must be driven low,

and tHWR_DELAY is the time that the digital host must wait between a

RESET falling edge and starting an SPI frame (see Table 2).

If the internal LDO supplies VDD, and the internal LDO is disabled

before a hardware reset, the internal LDO is enabled by the hard-

ware reset, and an additional delay is required to account for the

internal LDO output reaching the VDD minimum required voltage

(see the Power-On Resets (PORs) section).

Software Reset

To initiate a software reset, set the SW_RST_MSB bit and

SW_RST_LSB bit in the SPI_CONFIG_A register to 1. A software

reset reinitializes the state of all of the configuration registers listed

in the Register Information section to the default values, except for

the SPI_CONFIG_A register. When the software reset is complete,

the SW_RST_MSB bit and SW_RST_LSB bit automatically clear.

Figure 105 shows the timing requirements for performing a software

reset. tSWR_DELAY is the time that the digital host must wait between

the software reset and starting a new SPI frame (see Table 2).

Power-On Resets (PORs)

A POR is initiated when VDD or VIO is first supplied. When a

POR event is detected, the AD4697/AD4698 configuration registers

are initialized to the default values, but it is still recommended to

perform either a hardware reset or a software reset after a POR.

Figure 106 shows a timing diagram of a VDD POR where VIO is

already supplied. tPOR_VDD is the time that the digital host must wait

between VDD first being supplied and starting an SPI frame (see

Table 2). Figure 107 shows a timing diagram of a VIO POR where

VDD is already supplied. tPOR_VIO1 is the time that the digital host

must wait between VIO first being supplied and starting an SPI

frame (see Table 2).

When VDD is supplied by the internal LDO, the VDD POR is

triggered when the internal LDO output drives VDD to at least

the minimum VDD specification. The internal LDO output is only

enabled when both LDO_IN and VIO are supplied, and when the

LDO_EN bit in the setup register is set to 1 (see the Internal LDO

section).

Figure 108 shows a timing diagram of an LDO_IN POR where

VIO is already supplied. tPOR_LDO is the time that the digital host

must wait between LDO_IN first being supplied and starting an SPI

frame.

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