AD4697 datasheet(41/107 Pages) AD

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Data Sheet

AD4697/AD4698

THEORY OF OPERATION

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Rev. 0 | 41 of 107

input using any of the four channel sequencing modes results in

the same behavior as if the even numbered input were selected

instead. For this reason, it is recommended to only include the even

numbered input in the channel sequence.

Table 15. Register Settings for Channel Sequencing Modes

Channel Sequencing

Mode

STD_SEQ_EN NUM_SLOTS_AS

CYC_CTRL

Standard Sequencer

Don’t care

Advanced Sequencer

0x01 to 0x7F

Two-Cycle Command

0x00

Single-Cycle Command

0x00

Standard Sequencer

The standard sequencer automates progression through a preprog-

rammed set of enabled channels. The standard sequencer is the

simplest of the four channel sequencing modes and is ideal for

systems with fixed, static channel sequences.

The standard sequencer advances through each enabled channel

in ascending order and repeats the sequence until the device exits

conversion mode. The multiplexer channel is updated to the next

enabled channel each time a conversion result is ready. Figure 76

shows an example where the standard sequencer, three analog

inputs (IN0, IN2, and IN7), and the temperature sensor are enabled

in the sequence with no oversampling on any channel.

The bits in the STD_SEQ_CONFIG register control which chan-

nels are included in the channel sequence when the standard

sequencer is enabled. Each bit in the STD_SEQ_CONFIG register

corresponds to one of the eight analog inputs, and each channel is

enabled if its corresponding bit is set to 1. If the TEMP_EN bit in the

TEMP_CTRL register is set to 1, the temperature sensor is added

to the end of the sequence as well. For the example in

Figure 76, the value programmed into the STD_SEQ_CONFIG

To enable the standard sequencer, set the STD_SEQ_EN bit in the

SEQ_CTRL register to 1 and set the CYC_CTRL bit in the setup

default.

While the AD4697/AD4698 are in register configuration mode when

the STD_SEQ_EN bit in the SEQ_CTRL register is set to 1, the

multiplexer automatically connects the first enabled channel in the

sequence to the ADC core inputs, which allows the ADC to acquire

the signal on that channel even before the device enters conversion

mode.

When the standard sequencer is enabled, the control bits in the

CONFIG_IN0 register determine the configuration settings for all

IN0 to IN7 analog inputs (except for the polarity mode, which is

set for each INn analog input independently with the IN_MODE bit

in the corresponding CONFIG_INn register). Therefore, all analog

inputs have the same pin pairing options, analog input high-Z mode

enable settings, OSR settings, and threshold detection enable

settings.

The multiplexer does not advance to the next channel in the

sequence until the required number of conversions dictated by the

selected channel OSR setting is complete. For example, if the OSR

is set to 16, 16 CNV rising edges are required before the conver-

sion result is ready and the multiplexer selects the next channel in

the sequence. Figure 77 shows an example timing diagram where

the OSR for all channels is set to N. See the Oversampling and

Decimation section for more information.

When the standard sequencer is enabled, each enabled analog

input is sampled once per sequence iteration, which means each

analog input has the same effective sample rate. See the Effective

Channel Sample Rate section for more information.

Advanced Sequencer

The advanced sequencer automates progression through a pre-

programmed channel sequence where the order of the channels is

completely customizable. The advanced sequencer enables highly

flexible sequences of the channels with minimal digital overhead.

The advanced sequencer steps through a set of channel slots,

where each slot can be assigned to any of the eight analog

inputs, and sequences can be between 2 and 128 slots. The

sequence progresses through the enabled slots in ascending order

starting from Slot 0, and the sequence is repeated until the device

exits conversion mode. Figure 77 shows an example where the ad-

vanced sequencer is enabled with four slots enabled and assigned

to IN6, IN5, IN6, and IN3 with the temperature sensor enabled (with

no oversampling on any channel).

The number of slots in the sequence is set with the NUM_

SLOTS_AS bit field in the SEQ_CTRL register. Each slot channel

assignment is set with the SLOT_INX bit field in the AS_SLOTn

registers (located at Register Address 0x100 to Register Ad-

dress 0x17F), where AS_SLOT0 corresponds to Slot 0, AS_SLOT1

corresponds to Slot 1, and so on. Table 60 shows the values of

SLOT_INX for each of the eight analog inputs.

If the TEMP_EN bit in the TEMP_CTRL register is set to 1, the

temperature sensor is appended to the end of the sequence. The

temperature sensor cannot be selected with the SLOT_INX bit field

in the AS_SLOTn registers.

To enable the advanced sequencer, set the STD_SEQ_EN bit to 0,

set the CYC_CTRL bit to 0, and set the NUM_SLOTS_AS bit field

to any value between 1 and 127 (see Table 15).

While the AD4697/AD4698 are in register configuration mode when

the STD_SEQ_EN bit in the SEQ_CTRL register is set to 0, the

multiplexer automatically connects the channel specified in the

AS_SLOT0 register to the ADC core inputs, which allows the ADC

to acquire the signal on that channel even before the device enters

conversion mode.

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