AD4697 datasheet(62/107 Pages) AD

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Data Sheet

AD4697/AD4698

DIGITAL INTERFACE

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Rev. 0 | 62 of 107

AUTOCYCLE MODE

The AD4697/AD4698 can be configured to convert autonomously

on a user-programmed channel sequence, which is the ideal mode

of operation for system monitoring. When autocycle mode is ena-

bled, the AD4697/AD4698 generate an internal clock that acts as

the convert start signal, and the digital host is not required to gen-

erate a signal on the CNV signal. The internal convert start clock

is enabled when the AD4697/AD4698 enter conversion mode. The

internal convert start clock is disabled when the AD4697/AD4698

enter register configuration mode. Therefore, conversions only oc-

cur when the AD4697/AD4698 are in conversion mode.

Autocycle mode can be used in conjunction with the busy indicator,

threshold detection alerts, and the standard or advanced sequenc-

ers to reduce overhead for the digital host system. The threshold

detection alert indicator can be assigned to a general-purpose

pin and used as an interrupt to indicate a predetermined out of

bounds event. The threshold detection interrupt service routine

can optionally trigger an SPI instruction to read back the most

recent conversion result and exit conversion mode to determine

the specific type of out of bounds event using the alert indicator

registers (ALERT_STATUS1 to ALERT_STATUS2).

Autocycle mode is intended to be used with the standard sequencer

and advanced sequencer. Autocycle mode can optionally be used

with two-cycle command mode and single-cycle command mode,

but the digital host must transmit the 5-bit SDI commands for

selecting channels.

Autocycle mode is enabled when the AC_EN bit in the AC_CTRL

internal convert start signal. The convert start signal period is

selected with the AC_CYC bit field in the AC_CTRL register.

Table 24 shows the conversion period and corresponding sample

rates for each AC_CYC value.

Upon exiting autocycle mode and entering register configuration

mode, it is recommended to reset the AD4697/AD4698 before

reentering autocycle mode.

Table 24. Autocycle Mode Conversion Period Options

AC_CYC, Bits[2:0] Value

Conversion Period (μs)

Sample Rate (kSPS)

0x0

100

0x1

Table 24. Autocycle Mode Conversion Period Options

AC_CYC, Bits[2:0] Value

Conversion Period (μs)

Sample Rate (kSPS)

0x2

0x3

12.5

0x4

100

0x5

200

0x6

400

2.5

0x7

800

1.25

Note that the SPI transactions when autocycle mode is enabled

must adhere to the timing specifications of conversion mode (see

the Conversion Mode section and Table 2). Figure 125 shows a

timing diagram with the recommended general-purpose pin assign-

ments to synchronize the digital host with the AD4697/AD4698

with autocycle mode enabled. Either the alert indicator or the busy

indicator can be assigned to the general-purpose pins to determine

when the digital host can initiate the SPI transaction; however, only

the WLCSP options support assigning the alert and busy indicators

to separate the general-purpose pins. See the General-Purpose

Pins section for a description of configuring the general-purpose

pins to output the busy indicator and the alert indicator.

As shown in Figure 103, SPI transactions when using autocycle

mode must not start before tCONVERT has elapsed. The busy indica-

tor or the alert indicator must be used to ensure that the digital

host is synchronized to the internal convert start clock (see the

SPI Peripheral Synchronization in Autocycle Mode section). The

SCK rate must also be fast enough to complete the desired SPI

transaction before the next conversion begins (see the Conversion

Mode SPI Clock Frequency Requirements section).

The tACBSY specification dictates how long the busy indicator is

low between two conversions when autocycle mode is enabled.

The tSCKCNV specification dictates how much time must be given

between the final SCK rising edge of the SPI transaction and the

start of the next conversion.

The tCNVALT specification indicates the delay between the start

of the conversion and when the alert indicator state is updated.

A rising edge of the alert indicator does not directly imply that

the AD4697/AD4698 interface is ready for an SPI transaction but

can be used as an interrupt to trigger an SPI transaction if the

transaction is completed before the remainder of tCYC elapses.

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