AD4697 datasheet(90/107 Pages) AD

90 / 107 page

Data Sheet

AD4697/AD4698

analog.com

Rev. 0 | 90 of 107

Table 31. Configuration Register Names and Descriptions

Address

Name

Description

Length

Reset

Access

0x00C0 to 0x00CE

GAIN_INn

INn gain correction

Multibyte

0x8000

R/W

0x0100 to 0x017F

AS_SLOTn

Advanced sequencer slot

Single byte

0x00

R/W

SPI Configuration A Register

Address: 0x0000, Reset: 0x10, Name: SPI_CONFIG_A

Table 32. Bit Descriptions for SPI_CONFIG_A

Bits

Bit Name

Description

Reset

Access

SW_RST_MSB

Software Reset Bit (MSB). Setting both the SW_RST_MSB bit and SW_RST_LSB bit to 1 initiates a software reset

of the device, which resets all registers except the SPI_CONFIG_A register to the default power-up state (see the

Software Reset section).

0x0

R/W

RESERVED

Reserved.

0x0

ADDR_DIR

Address Direction Bit. This bit determines sequential addressing behavior when performing register reads and writes on

multiple bytes of data in a single data phase (see the Address Direction Options section).

0x0

R/W

0: selects the descending address option.

1: selects the ascending address option.

[4:1]

RESERVED

Reserved.

0x8

SW_RST_LSB

Software Reset Bit (LSB). Setting both the SW_RST_MSB and SW_RST_LSB bits to 1 initiates a software reset of the

device, which resets all registers except the SPI_CONFIG_A register to the default power-up state (see the Software

Reset section).

0x0

R/W

SPI Configuration B Register

Address: 0x0001, Reset: 0x00, Name: SPI_CONFIG_B

Table 33. Bit Descriptions for SPI_CONFIG_B

Bits

Bit Name

Description

Reset

Access

INST_MODE

Streaming or Single Instruction Mode Select Bit. This bit selects between streaming mode and single instruction mode

(see the Streaming Mode section and the Single Instruction Mode section).

0x0

R/W

0: enables streaming mode.

1: enables single instruction mode.

[6:4]

RESERVED

Reserved.

0x0

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