AD4697 datasheet(76/107 Pages) AD

76 / 107 page

Data Sheet

AD4697/AD4698

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 76 of 107

this option allows power cycling the internal reference buffer while

maintaining the desired VREF. To implement the internal reference

buffer power cycling scheme:

1. Disable and bypass the internal reference buffer when the ADC

is idle by setting REFBUF_EN to 0 and REFBUF_BP to 1.

2. Enable and reconnect the internal reference buffer when the

ADC needs to convert by setting REFBUF_EN to 1 and RE-

FBUF_BP to 0.

Reference Buffer Startup with Boost Mode

The reference buffer boost mode increases the maximum output

current of the internal reference buffer, therefore reducing the time

required for the internal reference buffer to charge CREF to the

target VREF. Figure 44 shows the charging of CREF vs. time when

boost mode is enabled vs. when it is disabled for common values of

CREF.

The internal reference buffer boost mode increases the peak AVDD

supply current while charging up CREF. For systems that require the

fastest possible device startup and can tolerate additional AVDD

peak supply current, it is recommended to enable the internal

reference buffer boost mode at the same time as enabling the

internal reference buffer (REFBUF_EN = REFBUF_BOOST = 1).

CONVERTING BETWEEN CODES AND VOLTS

The Transfer Function section describes the ideal transfer function

between the analog input voltage sampled by the AD4697/AD4698

ADC core and the resulting output code. The analog input voltage

(VINx) corresponding to each possible output code value (CODE-

OUT) is a function of the VREF voltage and the OSR setting and

polarity mode for the selected channel:

VINx=LSB×CODEOUT=VREF2N×CODEOUT (17)

where:

LSB is the LSB size.

N is the resolution of the output code.

The AD4697/AD4698 ADC core outputs 16-bit results (N = 16), but

the output code resolution is a function of the OSR selected for the

given channel (DR):

N=16+log4OSR

(18)

OSR can be set to 1, 4, 16, or 64, which correspond to an

output code resolution of 16, 17, 18, and 19, respectively. Table 9

through Table 12 show the negative and positive full-scale output

code values for each OSR. See the Oversampling and Decimation

section for details on configuring the OSR for each channel.

The polarity mode for the selected channel determines whether

CODEOUT uses straight binary or twos complement format. When

unipolar mode is selected, CODEOUT is in straight binary and is

therefore an unsigned integer value. When pseudobipolar mode is

selected, CODEOUT uses twos complement encoding and is there-

fore a signed integer value. See the Channel Configuration Options

for details on configuring the polarity mode for each channel.

The offset and gain correction settings for each channel modify the

transfer function of the AD4697/AD4698 to correct for first-order in-

accuracies in the system that cause the observed transfer function

to deviate from the ideal. Update the offset and gain fields for each

channel during system calibration. The Offset and Gain Correction

section describes how the offset and gain fields modify the AD4697/

AD4698 transfer function.

OVERSAMPLING FOR NOISE REDUCTION

The AD4697/AD4698 include on-chip oversampling and decimation

as a means to reduce the total effective Gaussian noise of the

system in the digital domain (see the Oversampling and Decimation

section). Assuming the AFE noise is Gaussian, the effective system

noise after oversampling (vn_OSR) is:

vn_OSR=vn_TOTALOSR

(19)

where:

Vn_TOTAL is the RTO system noise (defined in the Analog Front-End

Noise Considerations section).

OSR is the oversampling ratio setting for the given analog input

channel.

When the OSR is set to 1, no oversampling occurs, and the

effective noise remains vn_TOTAL. When OSR settings of 4, 16, and

64 are used, the noise is attenuated by a factor of 2, 4, and 8,

respectively.

The resulting dynamic range when utilizing oversampling (DROSR)

is as follows:

DROSR = DRtotal + 10logOSR (20)

where DRtotal is the system dynamic range for an OSR of 1 (defined

in the Analog Front-End Noise Considerations section).

The effective number of bits (ENOB) of the system increases by 1

every time the noise is halved. As a result, ENOB increases by

1 bit every time the OSR is increased by a factor of 4. To reflect

this, when an AD4697/AD4698 channel is configured with OSR

settings of 4, 16, or 64, the resolution of the conversion results for

that channel is extended to 17 bits, 18 bits, and 19 bits, respectively

(see the Transfer Function section and Serial Data Output Modes

section).

Note that oversampling and decimation only reduce voltage noise

for uniformly distributed Gaussian noise sources and have no effect

on other types of noise sources (such as 1/f noise).

DIGITAL INTERFACE OPERATION

Figure 112 shows a typical connection diagram of the AD4697/

AD4698 digital interface connected to a digital host. A single 4-wire

SPI-compatible host can operate the AD4697/AD4698, but some

AD4697 датащи(PDF) 76 Page - Analog Devices

AD4697 датащи(HTML) 76 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL