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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX6SDLCEC датащи(PDF) 126 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 126 Page - NXP Semiconductors |
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126 / 169 page  i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 126 NXP Semiconductors Electrical Characteristics NOTE • All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal AUDx_TXC/AUDx_RXC and/or the frame sync AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures. • All timings are on Audiomux Pads when SSI is being used for data transfer. • The terms, WL and BL, refer to Word Length (WL) and Bit Length(BL). • For internal Frame Sync operation using external clock, the frame sync timing is same as that of transmit data (for example, during AC97 mode of operation). Oversampling Clock Operation SS47 Oversampling clock period 15.04 — ns SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.0 ns Table 83. SSI Receiver Timing with Internal Clock (continued) ID Parameter Min Max Unit |
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