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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX6SDLCEC датащи(PDF) 151 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 151 Page - NXP Semiconductors |
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151 / 169 page  Package Information and Contact Assignments i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 151 LVDS1_TX2_N AB1 NVCC_LVDS2P5 — — LVDS1_TX2_N — — LVDS1_TX2_P AB2 NVCC_LVDS2P5 — ALT0 LVDS1_TX2_P Input Keeper LVDS1_TX3_N AA3 NVCC_LVDS2P5 — — LVDS1_TX3_N — — LVDS1_TX3_P AA4 NVCC_LVDS2P5 — ALT0 LVDS1_TX3_P Input Keeper MLB_CN A11 VDDHIGH_CAP — — MLB_CLK_N — — MLB_CP B11 VDDHIGH_CAP — — MLB_CLK_P — — MLB_DN B10 VDDHIGH_CAP — — MLB_DATA_N — — MLB_DP A10 VDDHIGH_CAP — — MLB_DATA_P — — MLB_SN A9 VDDHIGH_CAP — — MLB_SIG_N — — MLB_SP B9 VDDHIGH_CAP — — MLB_SIG_P — — NANDF_ALE A16 NVCC_NANDF GPIO ALT5 GPIO6_IO08 Input 100 k Ω pull-up NANDF_CLE C15 NVCC_NANDF GPIO ALT5 GPIO6_IO07 Input 100 k Ω pull-up NANDF_CS0 F15 NVCC_NANDF GPIO ALT5 GPIO6_IO11 Input 100 k Ω pull-up NANDF_CS1 C16 NVCC_NANDF GPIO ALT5 GPIO6_IO14 Input 100 k Ω pull-up NANDF_CS2 A17 NVCC_NANDF GPIO ALT5 GPIO6_IO15 Input 100 k Ω pull-up NANDF_CS3 D16 NVCC_NANDF GPIO ALT5 GPIO6_IO16 Input 100 k Ω pull-up NANDF_D0 A18 NVCC_NANDF GPIO ALT5 GPIO2_IO00 Input 100 k Ω pull-up NANDF_D1 C17 NVCC_NANDF GPIO ALT5 GPIO2_IO01 Input 100 k Ω pull-up NANDF_D2 F16 NVCC_NANDF GPIO ALT5 GPIO2_IO02 Input 100 k Ω pull-up NANDF_D3 D17 NVCC_NANDF GPIO ALT5 GPIO2_IO03 Input 100 k Ω pull-up NANDF_D4 A19 NVCC_NANDF GPIO ALT5 GPIO2_IO04 Input 100 k Ω pull-up NANDF_D5 B18 NVCC_NANDF GPIO ALT5 GPIO2_IO05 Input 100 k Ω pull-up NANDF_D6 E17 NVCC_NANDF GPIO ALT5 GPIO2_IO06 Input 100 k Ω pull-up NANDF_D7 C18 NVCC_NANDF GPIO ALT5 GPIO2_IO07 Input 100 k Ω pull-up NANDF_RB0 B16 NVCC_NANDF GPIO ALT5 GPIO6_IO10 Input 100 k Ω pull-up NANDF_WP_B E15 NVCC_NANDF GPIO ALT5 GPIO6_IO09 Input 100 k Ω pull-up ONOFF D12 VDD_SNVS_IN GPIO ALT0 SRC_ONOFF Input 100 k Ω pull-up PCIE_RXM B1 PCIE_VPH — — PCIE_RX_N — — PCIE_RXP B2 PCIE_VPH — — PCIE_RX_P — — PCIE_TXM A3 PCIE_VPH — — PCIE_TX_N — — PCIE_TXP B3 PCIE_VPH — — PCIE_TX_P — — PMIC_ON_REQ D11 VDD_SNVS_IN GPIO ALT0 SNVS_PMIC_ON_REQ Output Open drain with PU(100K) enable PMIC_STBY_REQ F11 VDD_SNVS_IN GPIO ALT0 CCM_PMIC_STBY_REQ Output Low POR_B C11 VDD_SNVS_IN GPIO ALT0 SRC_POR_B Input 100 k Ω pull-up RGMII_RD0 C24 NVCC_RGMII DDR ALT5 GPIO6_IO25 Input 100 k Ω pull-up Table 97. 21 x 21 mm Functional Contact Assignments (continued) Ball Name Ball Power Group Ball Type Out of Reset Condition1 Default Mode (Reset Mode) Default Function Input/ Output Value2 |
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