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TMS320DM643 датащи(PDF) 132 Page - Texas Instruments

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номер детали TMS320DM643
подробное описание детали  Video/Imaging Fixed-Point Digital Signal Processo
PDF  160 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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TMS320DM643 датащи(HTML) 132 Page - Texas Instruments

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VPxCLKINx
2
3
1
4
4
TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005
5.13.3.3
VCLKIN Timing (Video Display Mode)
Table 5-54. Timing Requirements for Video Display Mode for VPxCLKINx
(1) (see Figure 5-53)
–500
–600
NO.
UNIT
MIN
MAX
1
tc(VKI)
Cycle time, VPxCLKINx
9
ns
2
tw(VKIH)
Pulse duration, VPxCLKINx high
4.1
ns
3
tw(VKIL)
Pulse duration, VPxCLKINx low
4.1
ns
4
tt(VKI)
Transition time, VPxCLKINx
3
ns
(1)
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
Figure 5-53. Video Port Display VPxCLKINx Timing
5.13.3.4
Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx
and VPxCLKOUTx (Video Display Mode)
Table 5-55. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx (see Figure 5-54)
–500
–600
NO.
UNIT
MIN
MAX
13
tsu(VCTLV-VKIH)
Setup time, VPxCTLx valid before VPxCLKINx high
2.9
ns
14
th(VCTLV-VKIH)
Hold time, VPxCTLx valid after VPxCLKINx high
0.5
ns
15
tsu(VCTLV-VKOH)
Setup time, VPxCTLx valid before VPxCLKOUTx high(1)
7.4
ns
16
th(VCTLV-VKOH)
Hold time, VPxCTLx valid after VPxCLKOUTx high(1)
–0.9
ns
(1)
Assuming non-inverted VPxCLKOUTx signal.
DM643 Peripheral Information and Electrical Specifications
132



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