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Power Mode Controls

5685X Digital Signal Controller User Manual, Rev. 4

4-16

Freescale Semiconductor

4.9 Power Mode Controls

The Power Mode Control module controls movement between the three power modes supported

by the core:

1. Run mode provides full functionality

2. Functions disabled in Wait mode:

— execution of the core

— any unnecessary system clocks

3. Functions disabled in Stop mode:

— 56800E core

— all system clocks

— peripheral bus clock

— PLL optionally

— OSC optionally

All system clocks continue running in the Wait mode, allowing the DMA to operate in the Wait

mode. The time-based clock generated by the oscillator and Clock Generation Module (CGM)

are not affected by Low Power modes. Time based functions such as a Time-of-Day (TOD)

module and Computer Operating Properly (COP) module must be individually disabled for

maximum low-power effects. Likewise, Power Mode Controls do not affect pull-up/pull-down

resistor enabling. Power loss through input and bidirectional I/O cell pull-up/pull down resistors

can be eliminated by disabling the resistor in the software where supported, or in the case of

bidirectional I/O, by putting the cell in an output state and avoiding external contention.

When the core executes a Stop or Wait instruction it will wait until any stall or hold-off activity is

completed (c7WAITST has deasserted) then it asserts the p5STOP or p5WAIT SIM input and the

SIM will enter the corresponding Low Power mode. The SIM Control register also contains Stop

and Wait disable bits and feed the core. When asserted, these cause the core to ignore Stop and

Wait instructions, not assert p5STOP or p5WAIT.

Recovery from Stop or Wait mode to Run mode occurs if there is a pending enabled interrupt

(INT_PEND input asserts), or if there is a Debug mode request from the core due to a JTAG

initiated Debug mode entry request (JTDEBREQ input asserts), or if there is a Debug mode entry

request from the DE input pin (DE asserts). These three inputs are asynchronous so they are

metastabilized and re-timed to the system clock domain before use.

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