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DSP56857 датащи(PDF) 123 Page - Freescale Semiconductor, Inc

номер детали DSP56857
подробное описание детали  Digitial Signal Controller
PDF  662 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 датащи(HTML) 123 Page - Freescale Semiconductor, Inc

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Generated Clocks
System Integration Module (SIM), Rev. 4
Freescale Semiconductor
4-15
4.8 Generated Clocks
A description of the System Integrated Module (SIM) clock signals is shown in Table 4-8.
Table 4-8. SIM Clock Signals
Clock Output
Frequency
Enable Condition
Used By
CLK_SYS_DRAM
CLK_MSTR/2
((~HOLD OFF)¾ HOLD_DRAM) and (~Stop mode)
Data RAM
CLK_SYS_IPBB
CLK_MSTR/2
((~HOLD OFF) ¾HOLD_IPBB) and (~Stop mode)
IPBus Bridge
CLK_SYS_CPUCLK
CLK_MSTR/2
(~c7WAITST) and Run mode
Core
CLK_CPU_PCLK
CLK_MSTR/2
(~Stop mode) and ((~RST_CORE)¾
JHAWKCORETAP_EN ¾ EOnCE EBL
Note: JHAWKCORETAP_EN is re synchronized before
use
Core
EOnCE clock
CLK_CPU_NCLK
CLK_MSTR/2
(~Stop mode) and (~RST_CORE)¾ N1CLKEN)
Core
EOnCE clock
CLK_CPU_WCLK
CLK_SCAN
Always Enabled
Core
scan clock
CLK_SYS_GENRL
CLK_MSTR/2
(~HOLD OFF) and (~Stop mode)
SIM,
Program
RAM, SBC,
SAD, ROM
CLK_SYS_GENRL_INV
CLK_MSTR/2
(~HOLD OFF), (~Stop mode), and (TMODE_BIST)
RAM and
ROM BIST
CLK_CPU_CONT
CLK_MSTR/2
Always Enabled
SIM
CLK_PER_CONT
CLK_MSTR/4
(~Stop mode)
Peripherals
CLK_PER_CONT_INV
CLK_MSTR/4
(~Stop mode)
EMI
CLK_CLKOUT
CLK_MSTR/8
(~CLKOUT Disable)
Output pad
CLKOUT
PCLK_PHASE
—
Identical to CLK_PER_CONT, but phase shifted to rise
earlier
DMA, IPBB
HOLD OFF
—
HOLD_DRAM ¾ HOLD_IPBB
PAD, IPBB
C7WAITST
—
(HOLD OFF¾ CORE-STALL) and RST_CORE
Core



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