PIC18F4539-ESLASHMLSQTP datasheet(98/322 Pages) MICROCHIP

98 / 322 page

PIC18FXX39

DS30485A-page 96

Preliminary

 2002 Microchip Technology Inc.

9.6

Parallel Slave Port

The Parallel Slave Port is implemented on the 40-pin

devices only (PIC18F4X39).

PORTD also operates as an 8-bit wide Parallel Slave

Port, or microprocessor port, when control bit

PSPMODE (TRISE<4>) is set. It is asynchronously

readable and writable by the external world through RD

control input pin, RE0/AN5/RD and WR control input

pin, RE1/AN6/WR.

The PSP can directly interface to an 8-bit microproces-

sor data bus. The external microprocessor can read or

write the PORTD latch as an 8-bit latch. Setting bit

PSPMODE enables port pin RE0/AN5/RD to be the RD

input, RE1/AN6/WR to be the WR input and RE2/AN7/

CS to be the CS (chip select) input. For this functional-

ity, the corresponding data direction bits of the TRISE

(set). The A/D port configuration bits, PCFG2:PCFG0

(ADCON1<2:0>), must be set, which will configure pins

RE2:RE0 as digital I/O.

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

The PORTE I/O pins become control inputs for the

microprocessor port when bit PSPMODE (TRISE<4>)

is set. In this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

inputs), and the ADCON1 is configured for digital I/O.

In this mode, the input buffers are TTL.

FIGURE 9-10:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE

PORT)

FIGURE 9-11:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Data Bus

WR LATD

RDx

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to VDD and VSS.

TTL

PORTD

RD LATD

Data Latch

TRIS Latch

IBF

OBF

PSPIF

PORTD<7:0>

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