PIC18F4539-ESLASHMLSQTP datasheet(78/322 Pages) MICROCHIP

78 / 322 page

PIC18FXX39

DS30485A-page 76

Preliminary

 2002 Microchip Technology Inc.

8.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Inter-

rupt Enable registers (PIE1, PIE2). When IPEN = 0, the

PEIE bit must be set to enable any of these peripheral

interrupts.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

U-0

R/W-0

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

—TMR2IE(2)

TMR1IE

bit 7

bit 0

bit 7

PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

= Enables the PSP read/write interrupt

= Disables the PSP read/write interrupt

bit 6

ADIE: A/D Converter Interrupt Enable bit

= Enables the A/D interrupt

= Disables the A/D interrupt

bit 5

RCIE: USART Receive Interrupt Enable bit

= Enables the USART receive interrupt

= Disables the USART receive interrupt

bit 4

TXIE: USART Transmit Interrupt Enable bit

= Enables the USART transmit interrupt

= Disables the USART transmit interrupt

bit 3

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

= Enables the MSSP interrupt

= Disables the MSSP interrupt

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR2IE(2): TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

= Disables the TMR1 overflow interrupt

Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear.

2: This bit is reserved for use by the ProMPT kernel; do not alter its value.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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