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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F4539-E/MLSQTP датащи(PDF) 61 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP датащи(HTML) 61 Page - Microchip Technology |
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61 / 322 page  2002 Microchip Technology Inc. Preliminary DS30485A-page 59 PIC18FXX39 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) 5.5.2 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 5.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected RESET, the memory location just programmed should be verified and repro- grammed if needed.The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situ- ations, users can check the WRERR bit and rewrite the location. 5.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to FLASH program memory, the write initiate sequence must also be fol- lowed. See “Special Features of the CPU” (Section 20.0) for more detail. 5.6 FLASH Program Operation During Code Protection See “Special Features of the CPU” (Section 20.0) for details on code protection of FLASH program memory. TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY PROGRAM_MEMORY BSF EECON1,EEPGD ; point to FLASH program memory BCF EECON1,CFGS ; access FLASH program memory BSF EECON1,WREN ; enable write to memory BCF INTCON,GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW AAh MOVWF EECON2 ; write AAh BSF EECON1,WR ; start program (CPU stall) BSF INTCON,GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done BRA PROGRAM_LOOP BCF EECON1,WREN ; disable write to memory Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on All Other RESETS TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u EECON2 EEPROM Control Register2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — — — EEIP BCLIP LVDIP TMR3IP — ---1 1111 ---1 1111 PIR2 — — — EEIF BCLIF LVDIF TMR3IF — ---0 0000 ---0 0000 PIE2 — — —EEIE BCLIE LVDIE TMR3IE — ---0 0000 ---0 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access. |
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