PIC18F4539-ESLASHMLSQTP datasheet(71/322 Pages) MICROCHIP

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 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 69

PIC18FXX39

8.0

INTERRUPTS

The PIC18FXX39 devices have multiple interrupt

sources and an interrupt priority feature that allows

each interrupt source to be assigned a high priority

level or a low priority level. The high priority interrupt

vector is at 000008h and the low priority interrupt vector

is at 000018h. High priority interrupt events will

override any low priority interrupts that may be in

progress.

There are ten registers which are used to control

interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

It is recommended that the Microchip header files sup-

plied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

Each interrupt source, except INT0, has three bits to

control its operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts glo-

bally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set. Setting the GIEL

bit (INTCON<6>) enables all interrupts that have the

priority bit cleared. When the interrupt flag, enable bit

and appropriate global interrupt enable bit are set, the

interrupt will vector immediately to address 000008h or

000018h, depending on the priority level. Individual

interrupts can be disabled through their corresponding

enable bits.

While PIC18FXX39 devices have two interrupt priority

levels like other PIC18 microcontrollers, their allocation

is different. In these devices, the high priority interrupt

is used exclusively by the ProMPT kernel via the

Timer2 match interrupt. In order for the kernel to func-

tion properly, it is imperative that all other interrupts

either set as low priority (IPR bit = 0), or disabled.

When an interrupt is responded to, the Global Interrupt

Enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIEH or GIEL bits (as

applicable), which re-enables interrupts.

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

Note:

Disabling interrupts, or setting interrupts as

low priority, is not the same as disabling

interrupt priorities. The interrupt priority

levels must remain enabled (IPEN = 1).

Clearing the IPEN bit will result in erratic

operation of the ProMPT kernel.

Note:

Do not use the MOVFF instruction to modify

any of the Interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

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