PIC18F4539-ESLASHMLSQTP datasheet(41/322 Pages) MICROCHIP

41 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 39

PIC18FXX39

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

allowing up to 4096 bytes of data memory. The data

memory map is divided into 16 banks that contain 256

bytes each. The lower 4 bits of the Bank Select Regis-

ter (BSR<3:0>) select which bank will be accessed.

The upper 4 bits for the BSR are not implemented.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(FFFh) and extend downwards. Any remaining space

beyond the SFRs in the Bank may be implemented as

GPRs. GPRs start at the first location of Bank 0 and

grow upwards. Any read of an unimplemented location

will read as ‘0’s.

The organization of the data memory space for these

devices is shown in Figure 4-5 and Figure 4-6.

PIC18FX439 devices have 640 bytes of data RAM,

extending from Bank 0 to Bank 2 (000h through 27Fh).

The block of 128 bytes above this to the top of the bank

(280h to 2FFh) is used as data memory for the Motor

Control kernel, and is not available to the user. Reading

these locations will return random information that

reflects the kernel’s “scratch” data. Modifying the data

in these locations may disrupt the operation of the

ProMPT kernel.

PIC18FX539 devices have 1408 bytes of data RAM,

extending from Bank 0 to Bank 5 (000h through 57Fh).

As with the PIC18FX439 devices, the block of

128 bytes above this to the end of the bank (580h to

5FFh) is used by the Motor Control kernel.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the Data Memory map without banking.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing, or by the use of the MOVFF instruction. The

MOVFF

instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

provides a detailed description of the Access RAM.

4.9.1

GENERAL PURPOSE REGISTER

FILE

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates using a File Select

operation of indirect addressing is shown in

Section 4.12.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other RESETS.

Data RAM is available for use as GPR registers by all

instructions. The top half of Bank 15 (F80h to FFFh)

contains SFRs. All other banks of data memory contain

GPR registers, starting with Bank 0.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and Peripheral Modules for control-

ling the desired operation of the device. These regis-

ters are implemented as static RAM. A list of these

registers is given in Table 4-1 and Table 4-2.

The SFRs can be classified into two sets; those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The SFRs are typically distributed among the

peripherals whose functions they control. The unused

SFR locations will be unimplemented and read as '0's.

See Table 4-1 for addresses for the SFRs.

Note:

In this chapter and throughout this docu-

ment, certain SFR names and individual

bits are marked with an asterisk (*). This

denotes registers that are not implemented

in PIC18FXX39 devices, but whose names

are retained to maintain compatibility with

PIC18FXX2 devices. The designated bits

within these registers are reserved and

may be used by certain modules or the

Motor Control kernel. Users should not

write to these registers or alter these bit

values. Failure to do this may result in

erratic microcontroller operation.

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